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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
/*
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* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A55_H
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#define CORTEX_A55_H
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#include <lib/utils_def.h>
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/* Cortex-A55 MIDR for revision 0 */
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#define CORTEX_A55_MIDR U(0x410fd050)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)
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#define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)
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/*******************************************************************************
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* CPU Identification register specific definitions.
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******************************************************************************/
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#define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1
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#define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
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/* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */
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#define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1)
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/* Instruction patching registers */
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#define CPUPSELR_EL3 S3_6_C15_C8_0
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#define CPUPCR_EL3 S3_6_C15_C8_1
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#define CPUPOR_EL3 S3_6_C15_C8_2
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#define CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* CORTEX_A55_H */
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