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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
85 lines
3.8 KiB
C
85 lines
3.8 KiB
C
/*
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* Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A53_H
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#define CORTEX_A53_H
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#include <lib/utils_def.h>
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/* Cortex-A53 midr for revision 0 */
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#define CORTEX_A53_MIDR U(0x410FD030)
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 U(0x1)
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#define RETENTION_ENTRY_TICKS_8 U(0x2)
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#define RETENTION_ENTRY_TICKS_32 U(0x3)
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#define RETENTION_ENTRY_TICKS_64 U(0x4)
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#define RETENTION_ENTRY_TICKS_128 U(0x5)
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#define RETENTION_ENTRY_TICKS_256 U(0x6)
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#define RETENTION_ENTRY_TICKS_512 U(0x7)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
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#define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
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#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
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#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
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#define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
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#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
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#define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
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#define CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT U(13)
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#define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
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/*******************************************************************************
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* L2 Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
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#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
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#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
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#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
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#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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/*******************************************************************************
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* Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
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******************************************************************************/
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#ifndef __ASSEMBLER__
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DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A53_H */
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