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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
63 lines
2.6 KiB
C
63 lines
2.6 KiB
C
/*
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* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A72_H
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#define CORTEX_A72_H
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#include <lib/utils_def.h>
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/* Cortex-A72 midr for revision 0 */
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#define CORTEX_A72_MIDR U(0x410FD080)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_ECTLR p15, 1, c15
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#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_MERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_CPUACTLR p15, 0, c15
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#define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
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#define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
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#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
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#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
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#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
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#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
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#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A72_L2MERRSR p15, 3, c15
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#endif /* CORTEX_A72_H */
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