mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
edcece15c7
Initial version Signed-off-by: Margarita Glushkin <rutigl@gmail.com> Change-Id: If433d325a90b519ae5f02411865bffd368ff2824
230 lines
5 KiB
C
230 lines
5 KiB
C
/*
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* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
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*
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* Copyright (C) 2022-2023 Nuvoton Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ASM_ARCH_UART_H_
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#define __ASM_ARCH_UART_H_
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#ifndef __ASSEMBLY__
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struct npcmX50_uart {
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union {
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unsigned int rbr;
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unsigned int thr;
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unsigned int dll;
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};
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union {
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unsigned int ier;
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unsigned int dlm;
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};
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union {
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unsigned int iir;
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unsigned int fcr;
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};
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unsigned int lcr;
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unsigned int mcr;
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unsigned int lsr;
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unsigned int msr;
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unsigned int tor;
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};
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typedef enum {
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/*
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* UART0 is a general UART block without modem-I/O-control
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* connection to external signals.
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*/
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UART0_DEV = 0,
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/*
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* UART1-3 are each a general UART with modem-I/O-control
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* connection to external signals.
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*/
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UART1_DEV,
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UART2_DEV,
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UART3_DEV,
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} UART_DEV_T;
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typedef enum {
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/*
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* 0 0 0: Mode 1:
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* HSP1 connected to SI2,
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* HSP2 connected to UART2,
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* UART1 snoops HSP1,
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* UART3 snoops SI2
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*/
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UART_MUX_MODE1 = 0,
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/*
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* 0 0 1: Mode 2:
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* HSP1 connected to UART1,
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* HSP2 connected to SI2,
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* UART2 snoops HSP2,
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* UART3 snoops SI2
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*/
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UART_MUX_MODE2,
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/*
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* 0 1 0: Mode 3:
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* HSP1 connected to UART1,
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* HSP2 connected to UART2,
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* UART3 connected to SI2
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*/
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UART_MUX_MODE3,
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/*
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* 0 1 1: Mode 4:
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* HSP1 connected to SI1,
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* HSP2 connected to SI2,
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* UART1 snoops SI1,
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* UART3 snoops SI2,
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* UART2 snoops HSP1 (default)
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*/
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UART_MUX_MODE4,
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/*
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* 1 0 0: Mode 5:
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* HSP1 connected to SI1,
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* HSP2 connected to UART2,
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* UART1 snoops HSP1,
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* UART3 snoops SI1
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*/
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UART_MUX_MODE5,
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/*
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* 1 0 1: Mode 6:
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* HSP1 connected to SI1,
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* HSP2 connected to SI2,
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* UART1 snoops SI1,
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* UART3 snoops SI2,
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* UART2 snoops HSP2
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*/
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UART_MUX_MODE6,
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/*
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* 1 1 0: Mode 7:
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* HSP1 connected to SI1,
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* HSP2 connected to UART2,
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* UART1 snoops HSP1,
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* UART3 connected to SI2
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*/
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UART_MUX_MODE7,
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/* Skip UART mode configuration. */
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UART_MUX_RESERVED,
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/*
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* A SW option to allow config of UART
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* without touching the UART mux.
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*/
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UART_MUX_SKIP_CONFIG
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} UART_MUX_T;
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/*---------------------------------------------------------------------------*/
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/* Common baudrate definitions */
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/*---------------------------------------------------------------------------*/
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typedef enum {
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UART_BAUDRATE_110 = 110,
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UART_BAUDRATE_300 = 300,
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UART_BAUDRATE_600 = 600,
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UART_BAUDRATE_1200 = 1200,
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UART_BAUDRATE_2400 = 2400,
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UART_BAUDRATE_4800 = 4800,
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UART_BAUDRATE_9600 = 9600,
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UART_BAUDRATE_14400 = 14400,
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UART_BAUDRATE_19200 = 19200,
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UART_BAUDRATE_38400 = 38400,
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UART_BAUDRATE_57600 = 57600,
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UART_BAUDRATE_115200 = 115200,
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UART_BAUDRATE_230400 = 230400,
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UART_BAUDRATE_380400 = 380400,
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UART_BAUDRATE_460800 = 460800,
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} UART_BAUDRATE_T;
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/*---------------------------------------------------------------------------*/
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/* UART parity types */
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/*---------------------------------------------------------------------------*/
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typedef enum {
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UART_PARITY_NONE = 0,
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UART_PARITY_EVEN,
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UART_PARITY_ODD,
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} UART_PARITY_T;
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/*---------------------------------------------------------------------------*/
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/* Uart stop bits */
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/*---------------------------------------------------------------------------*/
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typedef enum {
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UART_STOPBIT_1 = 0x00,
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UART_STOPBIT_DYNAMIC,
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} UART_STOPBIT_T;
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enum FCR_RFITL_TYPE {
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FCR_RFITL_1B = 0x0,
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FCR_RFITL_4B = 0x4,
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FCR_RFITL_8B = 0x8,
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FCR_RFITL_14B = 0xC,
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};
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enum LCR_WLS_TYPE {
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LCR_WLS_5bit = 0x0,
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LCR_WLS_6bit = 0x1,
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LCR_WLS_7bit = 0x2,
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LCR_WLS_8bit = 0x3,
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};
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#define IER_DBGACK (1 << 4)
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#define IER_MSIE (1 << 3)
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#define IER_RLSE (1 << 2)
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#define IER_THREIE (1 << 1)
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#define IER_RDAIE (1 << 0)
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#define IIR_FMES (1 << 7)
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#define IIR_RFTLS (1 << 5)
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#define IIR_DMS (1 << 4)
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#define IIR_IID (1 << 1)
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#define IIR_NIP (1 << 0)
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#define FCR_RFITL_1B (0 << 4)
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#define FCR_RFITL_4B (4 << 4)
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#define FCR_RFITL_8B (8 << 4)
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#define FCR_RFITL_14B (12 << 4)
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#define FCR_DMS (1 << 3)
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#define FCR_TFR (1 << 2)
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#define FCR_RFR (1 << 1)
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#define FCR_FME (1 << 0)
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#define LCR_DLAB (1 << 7)
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#define LCR_BCB (1 << 6)
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#define LCR_SPE (1 << 5)
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#define LCR_EPS (1 << 4)
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#define LCR_PBE (1 << 3)
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#define LCR_NSB (1 << 2)
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#define LCR_WLS_8b (3 << 0)
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#define LCR_WLS_7b (2 << 0)
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#define LCR_WLS_6b (1 << 0)
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#define LCR_WLS_5b (0 << 0)
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#define MCR_LBME (1 << 4)
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#define MCR_OUT2 (1 << 3)
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#define MCR_RTS (1 << 1)
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#define MCR_DTR (1 << 0)
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#define LSR_ERR_RX (1 << 7)
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#define LSR_TE (1 << 6)
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#define LSR_THRE (1 << 5)
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#define LSR_BII (1 << 4)
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#define LSR_FEI (1 << 3)
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#define LSR_PEI (1 << 2)
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#define LSR_OEI (1 << 1)
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#define LSR_RFDR (1 << 0)
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#define MSR_DCD (1 << 7)
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#define MSR_RI (1 << 6)
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#define MSR_DSR (1 << 5)
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#define MSR_CTS (1 << 4)
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#define MSR_DDCD (1 << 3)
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#define MSR_DRI (1 << 2)
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#define MSR_DDSR (1 << 1)
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#define MSR_DCTS (1 << 0)
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#endif /* __ASSEMBLY__ */
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uintptr_t npcm845x_get_base_uart(UART_DEV_T dev);
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void CLK_ResetUART(void);
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int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate);
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#endif /* __ASM_ARCH_UART_H_ */
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