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https://github.com/ARM-software/arm-trusted-firmware.git
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ddaf02d171
This patch is used to implement sdmmc/nand/combo-phy driver to support Cadence IP for Agilex5 SoC FPGA. 1. Added SDMMC/NAND/COMBO-PHY support. 2. Updated product name -> Agilex5 3. Updated QSPI base address Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
256 lines
7.4 KiB
C
256 lines
7.4 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CDN_NAND_H
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#define CDN_NAND_H
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#include <drivers/cadence/cdns_combo_phy.h>
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/* NAND flash device information */
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typedef struct cnf_dev_info {
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uint8_t type;
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uint8_t nluns;
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uint8_t sector_cnt;
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uint16_t npages_per_block;
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uint16_t sector_size;
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uint16_t last_sector_size;
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uint16_t page_size;
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uint16_t spare_size;
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uint32_t nblocks_per_lun;
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uint32_t block_size;
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unsigned long long total_size;
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} cnf_dev_info_t;
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/* Shared Macros */
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/* Default values */
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#define CNF_DEF_VOL_ID 0
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#define CNF_DEF_DEVICE 0
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#define CNF_DEF_TRD 0
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#define CNF_READ_SINGLE_PAGE 1
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#define CNF_DEF_DELAY_US 500
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#define CNF_READ_INT_DELAY_US 10
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/* Work modes */
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#define CNF_WORK_MODE_CDMA 0
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#define CNF_WORK_MODE_PIO 1
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/* Command types */
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#define CNF_CT_SET_FEATURE 0x0100
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#define CNF_CT_RESET_ASYNC 0x1100
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#define CNF_CT_RESET_SYNC 0x1101
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#define CNF_CT_RESET_LUN 0x1102
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#define CNF_CT_ERASE 0x1000
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#define CNF_CT_PAGE_PROGRAM 0x2100
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#define CNF_CT_PAGE_READ 0x2200
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/* Interrupts enable or disable */
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#define CNF_INT_EN 1
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#define CNF_INT_DIS 0
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/* Device types */
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#define CNF_DT_UNKNOWN 0x00
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#define CNF_DT_ONFI 0x01
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#define CNF_DT_JEDEC 0x02
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#define CNF_DT_LEGACY 0x03
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/* Command and status registers */
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#define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE
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/* DMA maximum burst size 0-127*/
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#define CNF_DMA_BURST_SIZE_MAX 127
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/* DMA settings register field offsets */
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#define CNF_DMA_SETTINGS_BURST 0
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#define CNF_DMA_SETTINGS_OTE 16
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#define CNF_DMA_SETTINGS_SDMA_ERR 17
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#define CNF_DMA_MASTER_SEL 1
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#define CNF_DMA_SLAVE_SEL 0
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/* DMA FIFO trigger level register field offsets */
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#define CNF_FIFO_TLEVEL_POS 0
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#define CNF_FIFO_TLEVEL_DMA_SIZE 16
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#define CNF_DMA_PREFETCH_SIZE (1024 / 8)
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#define CNF_GET_CTRL_BUSY(x) (x & (1 << 8))
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#define CNF_GET_INIT_COMP(x) (x & (1 << 9))
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/* Command register0 field offsets */
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#define CNF_CMDREG0_CT 30
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#define CNF_CMDREG0_TRD 24
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#define CNF_CMDREG0_INTR 20
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#define CNF_CMDREG0_DMA 21
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#define CNF_CMDREG0_VOL 16
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#define CNF_CMDREG0_CMD 0
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#define CNF_CMDREG4_MEM 24
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/* Command status register field offsets */
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#define CNF_ECMD BIT(0)
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#define CNF_EECC BIT(1)
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#define CNF_EMAX BIT(2)
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#define CNF_EDEV BIT(12)
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#define CNF_EDQS BIT(13)
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#define CNF_EFAIL BIT(14)
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#define CNF_CMPLT BIT(15)
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#define CNF_EBUS BIT(16)
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#define CNF_EDI BIT(17)
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#define CNF_EPAR BIT(18)
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#define CNF_ECTX BIT(19)
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#define CNF_EPRO BIT(20)
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#define CNF_EIDX BIT(24)
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#define CNF_CMDREG_CMD_REG0 0x00
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#define CNF_CMDREG_CMD_REG1 0x04
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#define CNF_CMDREG_CMD_REG2 0x08
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#define CNF_CMDREG_CMD_REG3 0x0C
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#define CNF_CMDREG_CMD_STAT_PTR 0x10
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#define CNF_CMDREG_CMD_STAT 0x14
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#define CNF_CMDREG_CMD_REG4 0x20
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#define CNF_CMDREG_CTRL_STATUS 0x118
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#define CNF_CMDREG_TRD_STATUS 0x120
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#define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \
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+ (CNF_CMDREG_##_reg))
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/* Controller configuration registers */
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#define CNF_LSB16_MASK 0xFFFF
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#define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK)
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#define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK)
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#define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK)
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#define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK)
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#define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK)
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#define CNF_CTRLCFG_REG_BASE 0x10B80400
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#define CNF_CTRLCFG_TRANS_CFG0 0x00
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#define CNF_CTRLCFG_TRANS_CFG1 0x04
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#define CNF_CTRLCFG_LONG_POLL 0x08
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#define CNF_CTRLCFG_SHORT_POLL 0x0C
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#define CNF_CTRLCFG_DEV_STAT 0x10
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#define CNF_CTRLCFG_DEV_LAYOUT 0x24
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#define CNF_CTRLCFG_ECC_CFG0 0x28
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#define CNF_CTRLCFG_ECC_CFG1 0x2C
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#define CNF_CTRLCFG_MULTIPLANE_CFG 0x34
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#define CNF_CTRLCFG_CACHE_CFG 0x38
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#define CNF_CTRLCFG_DMA_SETTINGS 0x3C
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#define CNF_CTRLCFG_FIFO_TLEVEL 0x54
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#define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \
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+ (CNF_CTRLCFG_##_reg))
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/* Data integrity registers */
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#define CNF_DI_PAR_EN 0
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#define CNF_DI_CRC_EN 1
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#define CNF_DI_REG_BASE 0x10B80700
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#define CNF_DI_CONTROL 0x00
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#define CNF_DI_INJECT0 0x04
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#define CNF_DI_INJECT1 0x08
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#define CNF_DI_ERR_REG_ADDR 0x0C
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#define CNF_DI_INJECT2 0x10
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#define CNF_DI(_reg) (CNF_DI_REG_BASE \
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+ (CNF_DI_##_reg))
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/* Controller parameter registers */
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#define CNF_NTHREADS_MASK 0x07
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#define CNF_GET_NLUNS(x) (x & 0xFF)
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#define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03)
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#define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK))
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#define CNF_CTRLPARAM_REG_BASE 0x10B80800
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#define CNF_CTRLPARAM_VERSION 0x00
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#define CNF_CTRLPARAM_FEATURE 0x04
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#define CNF_CTRLPARAM_MFR_ID 0x08
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#define CNF_CTRLPARAM_DEV_AREA 0x0C
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#define CNF_CTRLPARAM_DEV_PARAMS0 0x10
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#define CNF_CTRLPARAM_DEV_PARAMS1 0x14
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#define CNF_CTRLPARAM_DEV_FEATUERS 0x18
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#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C
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#define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \
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+ (CNF_CTRLPARAM_##_reg))
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/* Protection mechanism registers */
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#define CNF_PROT_REG_BASE 0x10B80900
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#define CNF_PROT_CTRL0 0x00
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#define CNF_PROT_DOWN0 0x04
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#define CNF_PROT_UP0 0x08
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#define CNF_PROT_CTRL1 0x10
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#define CNF_PROT_DOWN1 0x14
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#define CNF_PROT_UP1 0x18
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#define CNF_PROT(_reg) (CNF_PROT_REG_BASE \
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+ (CNF_PROT_##_reg))
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/* Mini controller registers */
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#define CNF_MINICTRL_REG_BASE 0x10B81000
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/* Operation work modes */
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#define CNF_OPR_WORK_MODE_SDR 0
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#define CNF_OPR_WORK_MODE_NVDDR 1
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#define CNF_OPR_WORK_MODE_TOGGLE_NVDDR2_3 2
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#define CNF_OPR_WORK_MODE_RES 3
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/* Mini controller common settings register field offsets */
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#define CNF_CMN_SETTINGS_WR_WUP 20
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#define CNF_CMN_SETTINGS_RD_WUP 16
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#define CNF_CMN_SETTINGS_DEV16 8
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#define CNF_CMN_SETTINGS_OPR 0
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/* Async mode register field offsets */
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#define CNF_ASYNC_TIMINGS_TRH 24
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#define CNF_ASYNC_TIMINGS_TRP 16
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#define CNF_ASYNC_TIMINGS_TWH 8
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#define CNF_ASYNC_TIMINGS_TWP 0
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/* Mini controller DLL PHY controller register field offsets */
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#define CNF_DLL_PHY_RST_N 24
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#define CNF_DLL_PHY_EXT_WR_MODE 17
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#define CNF_DLL_PHY_EXT_RD_MODE 16
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#define CNF_MINICTRL_WP_SETTINGS 0x00
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#define CNF_MINICTRL_RBN_SETTINGS 0x04
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#define CNF_MINICTRL_CMN_SETTINGS 0x08
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#define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C
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#define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10
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#define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14
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#define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18
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#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C
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#define CNF_MINICTRL_SYNC_TIMINGS 0x20
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#define CNF_MINICTRL_DLL_PHY_CTRL 0x34
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#define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \
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+ (CNF_MINICTRL_##_reg))
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/*
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* @brief Nand IO MTD initialization routine
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*
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* @total_size: [out] Total size of the NAND flash device
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* @erase_size: [out] Minimum erase size of the NAND flash device
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* Return: 0 on success, a negative errno on failure
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*/
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int cdns_nand_init_mtd(unsigned long long *total_size,
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unsigned int *erase_size);
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/*
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* @brief Read bytes from the NAND flash device
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*
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* @offset: Byte offset to read from in device
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* @buffer: [out] Bytes read from device
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* @length: Number of bytes to read
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* @out_length: [out] Number of bytes read from device
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* Return: 0 on success, a negative errno on failure
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*/
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int cdns_nand_read(unsigned int offset, uintptr_t buffer,
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size_t length, size_t *out_length);
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/* NAND Flash Controller/Host initialization */
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int cdns_nand_host_init(void);
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#endif
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