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ddaf02d171
This patch is used to implement sdmmc/nand/combo-phy driver to support Cadence IP for Agilex5 SoC FPGA. 1. Added SDMMC/NAND/COMBO-PHY support. 2. Updated product name -> Agilex5 3. Updated QSPI base address Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
238 lines
6.4 KiB
C
238 lines
6.4 KiB
C
/*
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* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CDN_COMBOPHY_H
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#define CDN_COMBOPHY_H
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/* SRS */
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#define SDMMC_CDN_SRS02 0x8
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#define SDMMC_CDN_SRS03 0xC
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#define SDMMC_CDN_SRS04 0x10
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#define SDMMC_CDN_SRS05 0x14
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#define SDMMC_CDN_SRS06 0x18
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#define SDMMC_CDN_SRS07 0x1C
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#define SDMMC_CDN_SRS09 0x24
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#define SDMMC_CDN_SRS10 0x28
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#define SDMMC_CDN_SRS11 0x2C
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#define SDMMC_CDN_SRS12 0x30
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#define SDMMC_CDN_SRS13 0x34
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#define SDMMC_CDN_SRS14 0x38
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/* SRS03 */
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/* Response Type Select
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* Defines the expected response length.
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*/
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#define SDMMC_CDN_RTS 16
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/* Command CRC Check Enable
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* When set to 1, the host checks if the CRC field of the response is valid.
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* When 0, the CRC check is disabled and the CRC field of the response is ignored.
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*/
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#define SDMMC_CDN_CRCCE 19
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/* Command Index
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* This field contains a command number (index) of the command to be sent.
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*/
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#define SDMMC_CDN_CIDX 24
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/* SRS09 */
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/* Card Inserted
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* Indicates if the card is inserted inside the slot.
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*/
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#define SDMMC_CDN_CI 16
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/* SRS10 */
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/* Data Transfer Width
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* Bit used to configure DAT bus width to 1 or 4.
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*/
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#define SDMMC_CDN_DTW 1
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/* Extended Data Transfer Width
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* This bit is to enable/disable 8-bit DAT bus width mode.
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*/
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#define SDMMC_CDN_EDTW 5
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/* SD Bus Power for VDD1
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* When set to 1, the VDD1 voltage is supplied to card/device.
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*/
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#define SDMMC_CDN_BP 8
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/* SD Bus Voltage Select
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* This field is used to configure VDD1 voltage level.
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*/
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#define SDMMC_CDN_BVS 9
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/* SRS11 */
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/* Internal Clock Enable
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* This field is designated to controls (enable/disable) external clock generator.
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*/
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#define SDMMC_CDN_ICE 0
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/* Internal Clock Stable
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* When 1, indicates that the clock on sdmclk pin of the host is stable.
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* When 0, indicates that the clock is not stable .
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*/
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#define SDMMC_CDN_ICS 1
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/* SD Clock Enable
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* When set, SDCLK clock is enabled.
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* When clear, SDCLK clock is stopped.
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*/
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#define SDMMC_CDN_SDCE 2
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/* USDCLK Frequency Select
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* This is used to calculate frequency of USDCLK clock.
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*/
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#define SDMMC_CDN_USDCLKFS 6
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/* SDCLK Frequency Select
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* This is used to calculate frequency of SDCLK clock.
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*/
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#define SDMMC_CDN_SDCLKFS 8
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/* Data Timeout Counter Value
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* This value determines the interval by which DAT line timeouts are detected
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*/
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#define SDMMC_CDN_DTCV 16
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/* SRS12 */
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/* Command Complete
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* Generated when the end bit of the response is received.
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*/
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#define SDMMC_CDN_CC 0
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/* Transfer Complete
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* Generated when the transfer which uses the DAT line is complete.
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*/
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#define SDMMC_CDN_TC 1
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/* Error Interrupt
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* The software can check for an error by reading this single bit first.
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*/
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#define SDMMC_CDN_EINT 15
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/* SRS14 */
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/* Command Complete Interrupt Enable */
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#define SDMMC_CDN_CC_IE 0
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/* Transfer Complete Interrupt Enable */
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#define SDMMC_CDN_TC_IE 1
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/* DMA Interrupt Enable */
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#define SDMMC_CDN_DMAINT_IE 3
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/* Combo PHY DLL registers */
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#define CP_DLL_REG_BASE (0x10B92000)
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#define CP_DLL_DQ_TIMING_REG (0x00)
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#define CP_DLL_DQS_TIMING_REG (0x04)
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#define CP_DLL_GATE_LPBK_CTRL_REG (0x08)
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#define CP_DLL_MASTER_CTRL_REG (0x0C)
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#define CP_DLL_SLAVE_CTRL_REG (0x10)
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#define CP_DLL_IE_TIMING_REG (0x14)
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#define CP_DQ_TIMING_REG_SDR (0x00000002)
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#define CP_DQS_TIMING_REG_SDR (0x00100004)
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#define CP_GATE_LPBK_CTRL_REG_SDR (0x00D80000)
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#define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000)
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#define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000)
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#define CP_DLL(_reg) (CP_DLL_REG_BASE \
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+ (CP_DLL_##_reg))
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/* Control Timing Block registers */
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#define CP_CTB_REG_BASE (0x10B92080)
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#define CP_CTB_CTRL_REG (0x00)
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#define CP_CTB_TSEL_REG (0x04)
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#define CP_CTB_GPIO_CTRL0 (0x08)
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#define CP_CTB_GPIO_CTRL1 (0x0C)
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#define CP_CTB_GPIO_STATUS0 (0x10)
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#define CP_CTB_GPIO_STATUS1 (0x14)
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#define CP_CTRL_REG_SDR (0x00004040)
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#define CP_TSEL_REG_SDR (0x00000000)
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#define CP_CTB(_reg) (CP_CTB_REG_BASE \
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+ (CP_CTB_##_reg))
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/* Combo PHY */
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#define SDMMC_CDN_REG_BASE 0x10808200
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#define PHY_DQ_TIMING_REG 0x2000
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#define PHY_DQS_TIMING_REG 0x2004
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#define PHY_GATE_LPBK_CTRL_REG 0x2008
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#define PHY_DLL_MASTER_CTRL_REG 0x200C
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#define PHY_DLL_SLAVE_CTRL_REG 0x2010
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#define PHY_CTRL_REG 0x2080
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#define PHY_REG_ADDR_MASK 0xFFFF
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#define PHY_REG_DATA_MASK 0xFFFFFFFF
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/* PHY_DQS_TIMING_REG */
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#define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1
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#define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1
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#define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1
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#define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1
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/* PHY_GATE_LPBK_CTRL_REG */
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#define CP_SYNC_METHOD(x) ((x) << 31) //0x1
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#define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1
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#define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f
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#define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1
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#define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1
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/* PHY_DLL_MASTER_CTRL_REG */
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#define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1
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#define CP_DLL_START_POINT(x) ((x) << 0) //0xff
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/* PHY_DLL_SLAVE_CTRL_REG */
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#define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff
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#define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff
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#define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff
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#define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff
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/* PHY_DQ_TIMING_REG */
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#define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1
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#define CP_IO_MASK_END(x) ((x) << 27) //0x7
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#define CP_IO_MASK_START(x) ((x) << 24) //0x7
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#define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7
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/* PHY_CTRL_REG */
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#define CP_PHONY_DQS_TIMING_MASK 0x3F
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#define CP_PHONY_DQS_TIMING_SHIFT 4
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/* Shared Macros */
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#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \
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(SDMMC_CDN_##_reg))
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struct cdns_sdmmc_combo_phy {
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uint32_t cp_clk_wr_delay;
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uint32_t cp_clk_wrdqs_delay;
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uint32_t cp_data_select_oe_end;
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uint32_t cp_dll_bypass_mode;
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uint32_t cp_dll_locked_mode;
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uint32_t cp_dll_start_point;
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uint32_t cp_gate_cfg_always_on;
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uint32_t cp_io_mask_always_on;
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uint32_t cp_io_mask_end;
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uint32_t cp_io_mask_start;
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uint32_t cp_rd_del_sel;
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uint32_t cp_read_dqs_cmd_delay;
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uint32_t cp_read_dqs_delay;
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uint32_t cp_sw_half_cycle_shift;
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uint32_t cp_sync_method;
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uint32_t cp_underrun_suppress;
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uint32_t cp_use_ext_lpbk_dqs;
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uint32_t cp_use_lpbk_dqs;
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uint32_t cp_use_phony_dqs;
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uint32_t cp_use_phony_dqs_cmd;
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};
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/* Function Prototype */
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int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value,
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uint32_t phy_reg_data, uint32_t phy_reg_data_value);
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int cdns_sd_card_detect(void);
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int cdns_emmc_card_reset(void);
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#endif
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