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https://github.com/ARM-software/arm-trusted-firmware.git
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6c5c532051
Created a function to abort all pending NS DMA transactions to engage complete DMA protection. This call will be used by the subsequent DRTM implementation changes. Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com> Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com> Change-Id: I94992b54c570327d6746295073822a9c0ebdc85d
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/*
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* Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SMMU_V3_H
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#define SMMU_V3_H
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#include <stdint.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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/* SMMUv3 register offsets from device base */
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#define SMMU_CR0 U(0x0020)
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#define SMMU_CR0ACK U(0x0024)
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#define SMMU_GBPA U(0x0044)
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#define SMMU_S_IDR1 U(0x8004)
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#define SMMU_S_INIT U(0x803c)
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#define SMMU_S_GBPA U(0x8044)
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/*
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* TODO: SMMU_ROOT_PAGE_OFFSET is platform specific.
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* Currently defined as a command line model parameter.
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*/
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#if ENABLE_RME
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#define SMMU_ROOT_PAGE_OFFSET (PLAT_ARM_SMMUV3_ROOT_REG_OFFSET)
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#define SMMU_ROOT_IDR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0000)
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#define SMMU_ROOT_IIDR U(SMMU_ROOT_PAGE_OFFSET + 0x0008)
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#define SMMU_ROOT_CR0 U(SMMU_ROOT_PAGE_OFFSET + 0x0020)
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#define SMMU_ROOT_CR0ACK U(SMMU_ROOT_PAGE_OFFSET + 0x0024)
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#define SMMU_ROOT_GPT_BASE U(SMMU_ROOT_PAGE_OFFSET + 0x0028)
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#define SMMU_ROOT_GPT_BASE_CFG U(SMMU_ROOT_PAGE_OFFSET + 0x0030)
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#define SMMU_ROOT_GPF_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0038)
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#define SMMU_ROOT_GPT_CFG_FAR U(SMMU_ROOT_PAGE_OFFSET + 0x0040)
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#define SMMU_ROOT_TLBI U(SMMU_ROOT_PAGE_OFFSET + 0x0050)
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#define SMMU_ROOT_TLBI_CTRL U(SMMU_ROOT_PAGE_OFFSET + 0x0058)
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#endif /* ENABLE_RME */
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/* SMMU_CR0 and SMMU_CR0ACK register fields */
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#define SMMU_CR0_SMMUEN (1UL << 0)
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/* SMMU_GBPA register fields */
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#define SMMU_GBPA_UPDATE (1UL << 31)
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#define SMMU_GBPA_ABORT (1UL << 20)
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/* SMMU_S_IDR1 register fields */
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#define SMMU_S_IDR1_SECURE_IMPL (1UL << 31)
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/* SMMU_S_INIT register fields */
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#define SMMU_S_INIT_INV_ALL (1UL << 0)
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/* SMMU_S_GBPA register fields */
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#define SMMU_S_GBPA_UPDATE (1UL << 31)
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#define SMMU_S_GBPA_ABORT (1UL << 20)
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/* SMMU_ROOT_IDR0 register fields */
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#define SMMU_ROOT_IDR0_ROOT_IMPL (1UL << 0)
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/* SMMU_ROOT_CR0 register fields */
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#define SMMU_ROOT_CR0_GPCEN (1UL << 1)
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#define SMMU_ROOT_CR0_ACCESSEN (1UL << 0)
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int smmuv3_init(uintptr_t smmu_base);
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int smmuv3_security_init(uintptr_t smmu_base);
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int smmuv3_ns_set_abort_all(uintptr_t smmu_base);
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#endif /* SMMU_V3_H */
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