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https://github.com/ARM-software/arm-trusted-firmware.git
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4c117f6c49
This patch adds support for booting EL3 payloads on CSS platforms, for example Juno. In this scenario, the Trusted Firmware follows its normal boot flow up to the point where it would normally pass control to the BL31 image. At this point, it jumps to the EL3 payload entry point address instead. Before handing over to the EL3 payload, the data SCP writes for AP at the beginning of the Trusted SRAM is restored, i.e. we zero the first 128 bytes and restore the SCP Boot configuration. The latter is saved before transferring the BL30 image to SCP and is restored just after the transfer (in BL2). The goal is to make it appear that the EL3 payload is the first piece of software to run on the target. The BL31 entrypoint info structure is updated to make the primary CPU jump to the EL3 payload instead of the BL31 image. The mailbox is populated with the EL3 payload entrypoint address, which releases the secondary CPUs out of their holding pen (if the SCP has powered them on). The arm_program_trusted_mailbox() function has been exported for this purpose. The TZC-400 configuration in BL2 is simplified: it grants secure access only to the whole DRAM. Other security initialization is unchanged. This alternative boot flow is disabled by default. A new build option EL3_PAYLOAD_BASE has been introduced to enable it and provide the EL3 payload's entry point address. The build system has been modified such that BL31 and BL33 are not compiled and/or not put in the FIP in this case, as those images are not used in this boot flow. Change-Id: Id2e26fa57988bbc32323a0effd022ab42f5b5077
100 lines
3.5 KiB
C
100 lines
3.5 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm_def.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc400.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak plat_arm_security_setup
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/*******************************************************************************
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* Initialize the TrustZone Controller for ARM standard platforms.
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* Configure:
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* - Region 0 with no access;
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* - Region 1 with secure access only;
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* - the remaining DRAM regions access from the given Non-Secure masters.
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*
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* When booting an EL3 payload, this is simplified: we configure region 0 with
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* secure access only and do not enable any other region.
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******************************************************************************/
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void arm_tzc_setup(void)
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{
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INFO("Configuring TrustZone Controller\n");
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tzc_init(PLAT_ARM_TZC_BASE);
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/* Disable filters. */
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tzc_disable_filters();
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#ifndef EL3_PAYLOAD_BASE
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/* Region 0 set to no access by default */
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tzc_configure_region0(TZC_REGION_S_NONE, 0);
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/* Region 1 set to cover Secure part of DRAM */
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tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1,
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ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END,
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TZC_REGION_S_RDWR,
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0);
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/* Region 2 set to cover Non-Secure access to 1st DRAM address range.
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* Apply the same configuration to given filters in the TZC. */
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tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2,
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ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
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TZC_REGION_S_NONE,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
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tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3,
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ARM_DRAM2_BASE, ARM_DRAM2_END,
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TZC_REGION_S_NONE,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#else
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/* Allow secure access only to DRAM for EL3 payloads. */
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tzc_configure_region0(TZC_REGION_S_RDWR, 0);
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#endif /* EL3_PAYLOAD_BASE */
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/*
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* Raise an exception if a NS device tries to access secure memory
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* TODO: Add interrupt handling support.
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*/
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tzc_set_action(TZC_ACTION_ERR);
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/* Enable filters. */
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tzc_enable_filters();
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}
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void plat_arm_security_setup(void)
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{
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arm_tzc_setup();
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}
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