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https://github.com/ARM-software/arm-trusted-firmware.git
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4c0d039076
This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below: * Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible. In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked. Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
125 lines
4.7 KiB
ArmAsm
125 lines
4.7 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <css_def.h>
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.weak plat_secondary_cold_boot_setup
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.weak plat_get_my_entrypoint
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.globl css_calc_core_pos_swap_cluster
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.weak plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup(void);
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*
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* In the normal boot flow, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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*
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* When booting an EL3 payload, secondary CPUs are placed in a holding
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* pen, waiting for their mailbox to be populated. Note that all CPUs
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* share the same mailbox ; therefore, populating it will release all
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* CPUs from their holding pen. If finer-grained control is needed then
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* this should be handled in the code that secondary CPUs jump to.
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* ---------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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#ifndef EL3_PAYLOAD_BASE
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/* TODO: Implement secondary CPU cold boot setup on CSS platforms */
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cb_panic:
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b cb_panic
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#else
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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/* Wait until the mailbox gets populated */
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poll_mailbox:
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ldr x1, [x0]
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cbz x1, 1f
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br x1
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1:
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wfe
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b poll_mailbox
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#endif /* EL3_PAYLOAD_BASE */
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot. On CSS platforms, this distinction is based on the contents of
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* the Trusted Mailbox. It is initialised to zero by the SCP before the
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* AP cores are released from reset. Therefore, a zero mailbox means
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* it's a cold reset.
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*
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* This functions returns the contents of the mailbox, i.e.:
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* - 0 for a cold boot;
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* - the warm boot entrypoint for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------------
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* unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
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* Utility function to calculate the core position by
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* swapping the cluster order. This is necessary in order to
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* match the format of the boot information passed by the SCP
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* and read in plat_is_my_cpu_primary below.
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* -----------------------------------------------------------
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*/
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func css_calc_core_pos_swap_cluster
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
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add x0, x1, x0, LSR #6
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ret
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endfunc css_calc_core_pos_swap_cluster
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu (applicable ony after a cold boot)
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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ldr x1, =SCP_BOOT_CFG_ADDR
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ldr x1, [x1]
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ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
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#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
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cmp x0, x1
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cset w0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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