mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below: * Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible. In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked. Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
215 lines
7.6 KiB
ArmAsm
215 lines
7.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a53.h>
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#include <cortex_a57.h>
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#include <cortex_a72.h>
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#include <v2m_def.h>
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#include "../juno_def.h"
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.globl plat_reset_handler
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.globl plat_arm_calc_core_pos
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#define JUNO_REVISION(rev) REV_JUNO_R##rev
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#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
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#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \
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jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
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/* --------------------------------------------------------------------
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* Helper macro to jump to the given handler if the board revision
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* matches.
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* Expects the Juno board revision in x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_to_handler _revision, _handler
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cmp x0, #\_revision
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b.eq \_handler
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.endm
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/* --------------------------------------------------------------------
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* Helper macro that reads the part number of the current CPU and jumps
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* to the given label if it matches the CPU MIDR provided.
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*
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* Clobbers x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R0.
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*
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* Juno R0 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A57 processor cluster.
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*
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* This handler does the following:
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* - Implement workaround for defect id 831273 by enabling an event
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* stream every 65536 cycles.
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(0)
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/* --------------------------------------------------------------------
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* Enable the event stream every 65536 cycles
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* --------------------------------------------------------------------
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*/
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mov x0, #(0xf << EVNTI_SHIFT)
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orr x0, x0, #EVNTEN_BIT
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msr CNTKCTL_EL1, x0
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/* --------------------------------------------------------------------
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* Nothing else to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A53_MIDR, 1f
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
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msr L2CTLR_EL1, x0
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1:
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isb
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ret
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endfunc JUNO_HANDLER(0)
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R1.
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*
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* Juno R1 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A57 processor cluster.
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*
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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*
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* Note that:
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* - The default value for the L2 Tag RAM latency for Cortex-A57 is
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* suitable.
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* - Defect #831273 doesn't affect Juno R1.
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(1)
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/* --------------------------------------------------------------------
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* Nothing to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A57_MIDR, A57
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ret
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A57:
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
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msr L2CTLR_EL1, x0
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isb
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ret
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endfunc JUNO_HANDLER(1)
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R2.
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*
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* Juno R2 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A72 processor cluster.
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*
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
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* - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
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*
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* Note that:
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* - Defect #831273 doesn't affect Juno R2.
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(2)
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/* --------------------------------------------------------------------
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* Nothing to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A72_MIDR, A72
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ret
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A72:
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/* --------------------------------------------------------------------
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* Cortex-A72 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
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msr L2CTLR_EL1, x0
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isb
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ret
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endfunc JUNO_HANDLER(2)
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Determine the Juno board revision and call the appropriate reset
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* handler.
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* --------------------------------------------------------------------
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*/
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func plat_reset_handler
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/* Read the V2M SYS_ID register */
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mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
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ldr w1, [x0]
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/* Extract board revision from the SYS_ID */
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ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4
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JUMP_TO_HANDLER_IF_JUNO_R(0)
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JUMP_TO_HANDLER_IF_JUNO_R(1)
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JUMP_TO_HANDLER_IF_JUNO_R(2)
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/* Board revision is not supported */
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bl plat_panic_handler
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endfunc plat_reset_handler
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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* Helper function to calculate the core position.
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* -----------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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b css_calc_core_pos_swap_cluster
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endfunc plat_arm_calc_core_pos
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