mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-24 22:05:40 +00:00
4bdb1a7a6a
This commit adds authentication binary support for STM32MP1. It prints the bootrom authentication result if signed image is used and authenticates the next loaded STM32 images. It also enables the dynamic translation table support (PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51
344 lines
11 KiB
C
344 lines
11 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_DEF_H
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#define STM32MP1_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/st/stm32mp1_rcc.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#ifndef __ASSEMBLER__
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#include <drivers/st/bsec.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <boot_api.h>
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#include <stm32mp_auth.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shres_helpers.h>
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#include <stm32mp1_dbgmcu.h>
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#include <stm32mp1_private.h>
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#endif
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/*******************************************************************************
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* CHIP ID
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******************************************************************************/
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#define STM32MP157C_PART_NB U(0x05000000)
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#define STM32MP157A_PART_NB U(0x05000001)
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#define STM32MP153C_PART_NB U(0x05000024)
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#define STM32MP153A_PART_NB U(0x05000025)
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#define STM32MP151C_PART_NB U(0x0500002E)
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#define STM32MP151A_PART_NB U(0x0500002F)
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#define STM32MP1_REV_B U(0x2000)
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/*******************************************************************************
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* PACKAGE ID
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******************************************************************************/
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#define PKG_AA_LFBGA448 U(4)
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#define PKG_AB_LFBGA354 U(3)
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#define PKG_AC_TFBGA361 U(2)
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#define PKG_AD_TFBGA257 U(1)
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/*******************************************************************************
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* STM32MP1 memory map related constants
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******************************************************************************/
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#define STM32MP_ROM_BASE U(0x00000000)
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#define STM32MP_ROM_SIZE U(0x00020000)
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#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
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#define STM32MP_SYSRAM_SIZE U(0x00040000)
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/* DDR configuration */
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#define STM32MP_DDR_BASE U(0xC0000000)
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#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#endif
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/* DDR power initializations */
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#ifndef __ASSEMBLER__
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enum ddr_type {
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STM32MP_DDR3,
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STM32MP_LPDDR2,
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STM32MP_LPDDR3
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};
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#endif
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/* Section used inside TF binaries */
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#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
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/* 256 Octets reserved for header */
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#define STM32MP_HEADER_SIZE U(0x00000100)
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#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE)
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#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
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(STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE))
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_BL32_SIZE U(0)
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#define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE
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#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
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STM32MP_OPTEE_BASE)
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#else
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
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#else
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#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
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#endif
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#endif
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#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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STM32MP_BL32_SIZE)
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#ifdef AARCH32_SP_OPTEE
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */
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#else
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#define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */
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#endif
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#else
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#if STACK_PROTECTOR_ENABLED
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#define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */
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#else
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#define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */
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#endif
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#endif
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#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
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STM32MP_BL2_SIZE)
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/* BL2 and BL32/sp_min require 5 tables */
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#define MAX_XLAT_TABLES 5
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL2)
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#define MAX_MMAP_REGIONS 11
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#endif
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#if defined(IMAGE_BL32)
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#define MAX_MMAP_REGIONS 6
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#endif
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/* DTB initialization value */
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#define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */
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#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_DTB_SIZE)
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
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/*******************************************************************************
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* STM32MP1 device/io map related constants (used for MMU)
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******************************************************************************/
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#define STM32MP1_DEVICE1_BASE U(0x40000000)
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#define STM32MP1_DEVICE1_SIZE U(0x40000000)
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#define STM32MP1_DEVICE2_BASE U(0x80000000)
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#define STM32MP1_DEVICE2_SIZE U(0x40000000)
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/*******************************************************************************
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* STM32MP1 RCC
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******************************************************************************/
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#define RCC_BASE U(0x50000000)
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/*******************************************************************************
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* STM32MP1 PWR
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******************************************************************************/
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#define PWR_BASE U(0x50001000)
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/*******************************************************************************
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* STM32MP1 GPIO
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******************************************************************************/
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#define GPIOA_BASE U(0x50002000)
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#define GPIOB_BASE U(0x50003000)
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#define GPIOC_BASE U(0x50004000)
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#define GPIOD_BASE U(0x50005000)
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#define GPIOE_BASE U(0x50006000)
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#define GPIOF_BASE U(0x50007000)
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#define GPIOG_BASE U(0x50008000)
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#define GPIOH_BASE U(0x50009000)
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#define GPIOI_BASE U(0x5000A000)
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#define GPIOJ_BASE U(0x5000B000)
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#define GPIOK_BASE U(0x5000C000)
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#define GPIOZ_BASE U(0x54004000)
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#define GPIO_BANK_OFFSET U(0x1000)
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/* Bank IDs used in GPIO driver API */
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#define GPIO_BANK_A U(0)
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#define GPIO_BANK_B U(1)
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#define GPIO_BANK_C U(2)
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#define GPIO_BANK_D U(3)
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#define GPIO_BANK_E U(4)
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#define GPIO_BANK_F U(5)
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#define GPIO_BANK_G U(6)
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#define GPIO_BANK_H U(7)
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#define GPIO_BANK_I U(8)
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#define GPIO_BANK_J U(9)
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#define GPIO_BANK_K U(10)
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#define GPIO_BANK_Z U(25)
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#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
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/*******************************************************************************
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* STM32MP1 UART
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******************************************************************************/
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#define USART1_BASE U(0x5C000000)
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#define USART2_BASE U(0x4000E000)
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#define USART3_BASE U(0x4000F000)
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#define UART4_BASE U(0x40010000)
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#define UART5_BASE U(0x40011000)
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#define USART6_BASE U(0x44003000)
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#define UART7_BASE U(0x40018000)
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#define UART8_BASE U(0x40019000)
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#define STM32MP_UART_BAUDRATE U(115200)
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/* For UART crash console */
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#define STM32MP_DEBUG_USART_BASE UART4_BASE
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/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
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#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
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#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
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#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
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#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
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#define DEBUG_UART_TX_GPIO_PORT 11
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#define DEBUG_UART_TX_GPIO_ALTERNATE 6
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#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
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#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
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#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
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#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
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/*******************************************************************************
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* STM32MP1 TZC (TZ400)
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******************************************************************************/
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#define STM32MP1_TZC_BASE U(0x5C006000)
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#define STM32MP1_TZC_A7_ID U(0)
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#define STM32MP1_TZC_M4_ID U(1)
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#define STM32MP1_TZC_LCD_ID U(3)
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#define STM32MP1_TZC_GPU_ID U(4)
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#define STM32MP1_TZC_MDMA_ID U(5)
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#define STM32MP1_TZC_DMA_ID U(6)
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#define STM32MP1_TZC_USB_HOST_ID U(7)
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#define STM32MP1_TZC_USB_OTG_ID U(8)
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#define STM32MP1_TZC_SDMMC_ID U(9)
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#define STM32MP1_TZC_ETH_ID U(10)
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#define STM32MP1_TZC_DAP_ID U(15)
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#define STM32MP1_FILTER_BIT_ALL U(3)
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/*******************************************************************************
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* STM32MP1 SDMMC
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******************************************************************************/
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#define STM32MP_SDMMC1_BASE U(0x58005000)
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#define STM32MP_SDMMC2_BASE U(0x58007000)
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#define STM32MP_SDMMC3_BASE U(0x48004000)
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#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
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#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
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#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
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#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
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#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
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/*******************************************************************************
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* STM32MP1 BSEC / OTP
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******************************************************************************/
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#define STM32MP1_OTP_MAX_ID 0x5FU
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#define STM32MP1_UPPER_OTP_START 0x20U
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#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
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/* OTP offsets */
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#define DATA0_OTP U(0)
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#define PART_NUMBER_OTP U(1)
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#define PACKAGE_OTP U(16)
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#define HW2_OTP U(18)
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/* OTP mask */
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/* DATA0 */
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#define DATA0_OTP_SECURED BIT(6)
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/* PART NUMBER */
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#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
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#define PART_NUMBER_OTP_PART_SHIFT 0
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/* PACKAGE */
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#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
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#define PACKAGE_OTP_PKG_SHIFT 27
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/* IWDG OTP */
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#define HW2_OTP_IWDG_HW_POS U(3)
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#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
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#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
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/* HW2 OTP */
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#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
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/*******************************************************************************
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* STM32MP1 TAMP
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******************************************************************************/
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#define TAMP_BASE U(0x5C00A000)
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
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static inline uint32_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP1 DDRCTRL
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******************************************************************************/
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#define DDRCTRL_BASE U(0x5A003000)
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/*******************************************************************************
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* STM32MP1 DDRPHYC
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******************************************************************************/
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#define DDRPHYC_BASE U(0x5A004000)
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/*******************************************************************************
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* STM32MP1 IWDG
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******************************************************************************/
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#define IWDG_MAX_INSTANCE U(2)
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#define IWDG1_INST U(0)
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#define IWDG2_INST U(1)
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#define IWDG1_BASE U(0x5C003000)
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#define IWDG2_BASE U(0x5A002000)
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/*******************************************************************************
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* STM32MP1 I2C4
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******************************************************************************/
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#define I2C4_BASE U(0x5C002000)
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/*******************************************************************************
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* STM32MP1 DBGMCU
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******************************************************************************/
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#define DBGMCU_BASE U(0x50081000)
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/*******************************************************************************
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* Device Tree defines
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******************************************************************************/
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#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
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#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
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#define DT_PWR_COMPAT "st,stm32mp1-pwr"
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#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
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#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
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#endif /* STM32MP1_DEF_H */
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