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8b81a39e28
S32G274ARDB2 is a development board to showcase the capabilities of the S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs of DDR, accelerators for automotive networking and many other peripherals. The added support is minimal and only includes the BL2 stage, with no MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies BL31 and BL33 from FIP to their designated addresses. Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/desc_image_load.h>
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#include <plat/common/platform.h>
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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.ep_info.pc = BL31_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.image_info.image_base = BL31_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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NON_SECURE | EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, 0),
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.image_info.image_max_size = BL33_LIMIT - BL33_BASE,
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.image_info.image_base = BL33_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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