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https://github.com/ARM-software/arm-trusted-firmware.git
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8b81a39e28
S32G274ARDB2 is a development board to showcase the capabilities of the S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs of DDR, accelerators for automotive networking and many other peripherals. The added support is minimal and only includes the BL2 stage, with no MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies BL31 and BL33 from FIP to their designated addresses. Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Dan Nica <dan.nica@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/desc_image_load.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <plat_console.h>
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#include <plat_io_storage.h>
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#define SIUL2_PC09_MSCR UL(0x4009C2E4)
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#define SIUL2_PC10_MSCR UL(0x4009C2E8)
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#define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40)
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#define LIN0_TX_MSCR_CFG U(0x00214001)
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#define LIN0_RX_MSCR_CFG U(0x00094000)
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#define LIN0_RX_IMCR_CFG U(0x00000002)
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struct bl_load_info *plat_get_bl_image_load_info(void)
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{
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return get_bl_load_info_from_mem_params_desc();
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}
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struct bl_params *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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void bl2_platform_setup(void)
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{
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}
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static void linflex_config_pinctrl(void)
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{
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/* set PC09 - MSCR[41] - for UART0 TXD */
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mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
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/* set PC10 - MSCR[42] - for UART0 RXD */
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mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
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/* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
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mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
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}
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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linflex_config_pinctrl();
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console_s32g2_register();
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plat_s32g2_io_setup();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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