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https://github.com/ARM-software/arm-trusted-firmware.git
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e73c3c3a6c
Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core cold boot without MMU and PSCI services. Change-Id: I8a10fd62f3cc9430083758043ea82e3803f61060 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com> Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <plat/common/common_def.h>
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#define PLATFORM_STACK_SIZE U(0x1000)
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/* Caches */
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/* CPU Topology */
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#define PLATFORM_CORE_COUNT U(4)
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_PRIMARY_CPU U(0)
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#define PLATFORM_MPIDR_CPU_MASK_BITS U(1)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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/* Power Domains */
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_PWR_LVL_STATES U(2)
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/* BL2 stage */
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#define BL2_BASE UL(0x34078000)
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#define BL2_LIMIT UL(0x34100000)
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/* BL31 stage */
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#define BL31_BASE UL(0x34200000)
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#define BL31_LIMIT UL(0x34300000)
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/* It is a dummy value for now, given the missing DDR */
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#define BL33_BASE UL(0x34500000)
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#define BL33_LIMIT UL(0x345FF000)
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36)
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/* We'll be doing a 1:1 mapping anyway */
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36)
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#define MAX_MMAP_REGIONS U(8)
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#define MAX_XLAT_TABLES U(32)
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/* Console settings */
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#define UART_BASE UL(0x401C8000)
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#define UART_BAUDRATE U(115200)
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/* FIRC clock */
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#define UART_CLOCK_HZ U(48000000)
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#define S32G_FIP_BASE UL(0x34100000)
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#define S32G_FIP_SIZE UL(0x100000)
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#define MAX_IO_HANDLES U(2)
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#define MAX_IO_DEVICES U(2)
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/* GIC settings */
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#define S32G_GIC_BASE UL(0x50800000)
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#define PLAT_GICD_BASE S32G_GIC_BASE
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#define PLAT_GICR_BASE (S32G_GIC_BASE + UL(0x80000))
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/* Generic timer frequency; this goes directly into CNTFRQ_EL0.
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* Its end-value is 5MHz; this is based on the assumption that
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* GPR00[CA53_COUNTER_CLK_DIV_VAL] contains the reset value of 0x7, hence
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* producing a divider value of 8, applied to the FXOSC frequency of 40MHz.
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*/
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#define COUNTER_FREQUENCY U(5000000)
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#endif /* PLATFORM_DEF_H */
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