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https://github.com/ARM-software/arm-trusted-firmware.git
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4a826ddad8
The runtime exception handling assembler code used magic numbers for saving and restoring the general purpose register context on stack memory. The memory is interpreted as a 'gp_regs' structure and the magic numbers are offsets to members of this structure. This patch replaces the magic number offsets with constants. It also adds compile time assertions to prevent an incorrect assembler view of this structure. Change-Id: Ibf125bfdd62ba3a33e58c5f1d71f8c229720781c
389 lines
8.1 KiB
ArmAsm
389 lines
8.1 KiB
ArmAsm
/*
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* Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <runtime_svc.h>
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.globl save_regs
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.globl restore_regs
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.globl enable_irq
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.globl disable_irq
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.globl enable_fiq
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.globl disable_fiq
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.globl enable_serror
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.globl disable_serror
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.globl enable_debug_exceptions
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.globl disable_debug_exceptions
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.globl read_daif
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.globl write_daif
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.globl read_spsr
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.globl read_spsr_el1
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.globl read_spsr_el2
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.globl read_spsr_el3
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.globl write_spsr
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.globl write_spsr_el1
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.globl write_spsr_el2
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.globl write_spsr_el3
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.globl read_elr
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.globl read_elr_el1
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.globl read_elr_el2
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.globl read_elr_el3
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.globl write_elr
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.globl write_elr_el1
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.globl write_elr_el2
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.globl write_elr_el3
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.globl get_afflvl_shift
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.globl mpidr_mask_lower_afflvls
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.globl dsb
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.globl isb
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.globl sev
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.globl wfe
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.globl wfi
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.globl eret
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.globl smc
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.globl zeromem16
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.globl memcpy16
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.section .text, "ax"
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save_regs:; .type save_regs, %function
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sub sp, sp, #GPREGS_FP_OFF
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stp x0, x1, [sp, #GPREGS_X0_OFF]
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stp x2, x3, [sp, #GPREGS_X2_OFF]
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stp x4, x5, [sp, #GPREGS_X4_OFF]
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stp x6, x7, [sp, #GPREGS_X6_OFF]
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stp x8, x9, [sp, #GPREGS_X8_OFF]
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stp x10, x11, [sp, #GPREGS_X10_OFF]
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stp x12, x13, [sp, #GPREGS_X12_OFF]
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stp x14, x15, [sp, #GPREGS_X14_OFF]
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stp x16, x17, [sp, #GPREGS_X16_OFF]
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stp x18, x19, [sp, #GPREGS_X18_OFF]
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stp x20, x21, [sp, #GPREGS_X20_OFF]
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stp x22, x23, [sp, #GPREGS_X22_OFF]
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stp x24, x25, [sp, #GPREGS_X24_OFF]
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stp x26, x27, [sp, #GPREGS_X26_OFF]
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mrs x0, sp_el0
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stp x28, x0, [sp, #GPREGS_X28_OFF]
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mrs x0, spsr_el3
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str x0, [sp, #GPREGS_SPSR_OFF]
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ret
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restore_regs:; .type restore_regs, %function
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ldr x9, [sp, #GPREGS_SPSR_OFF]
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msr spsr_el3, x9
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ldp x28, x9, [sp, #GPREGS_X28_OFF]
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msr sp_el0, x9
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ldp x26, x27, [sp, #GPREGS_X26_OFF]
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ldp x24, x25, [sp, #GPREGS_X24_OFF]
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ldp x22, x23, [sp, #GPREGS_X22_OFF]
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ldp x20, x21, [sp, #GPREGS_X20_OFF]
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ldp x18, x19, [sp, #GPREGS_X18_OFF]
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ldp x16, x17, [sp, #GPREGS_X16_OFF]
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ldp x14, x15, [sp, #GPREGS_X14_OFF]
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ldp x12, x13, [sp, #GPREGS_X12_OFF]
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ldp x10, x11, [sp, #GPREGS_X10_OFF]
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ldp x8, x9, [sp, #GPREGS_X8_OFF]
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ldp x6, x7, [sp, #GPREGS_X6_OFF]
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ldp x4, x5, [sp, #GPREGS_X4_OFF]
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ldp x2, x3, [sp, #GPREGS_X2_OFF]
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ldp x0, x1, [sp, #GPREGS_X0_OFF]
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add sp, sp, #GPREGS_FP_OFF
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ret
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get_afflvl_shift:; .type get_afflvl_shift, %function
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cmp x0, #3
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cinc x0, x0, eq
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mov x1, #MPIDR_AFFLVL_SHIFT
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lsl x0, x0, x1
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ret
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mpidr_mask_lower_afflvls:; .type mpidr_mask_lower_afflvls, %function
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cmp x1, #3
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cinc x1, x1, eq
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mov x2, #MPIDR_AFFLVL_SHIFT
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lsl x2, x1, x2
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lsr x0, x0, x2
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lsl x0, x0, x2
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ret
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/* -----------------------------------------------------
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* Asynchronous exception manipulation accessors
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* -----------------------------------------------------
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*/
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enable_irq:; .type enable_irq, %function
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msr daifclr, #DAIF_IRQ_BIT
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ret
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enable_fiq:; .type enable_fiq, %function
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msr daifclr, #DAIF_FIQ_BIT
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ret
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enable_serror:; .type enable_serror, %function
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msr daifclr, #DAIF_ABT_BIT
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ret
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enable_debug_exceptions:
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msr daifclr, #DAIF_DBG_BIT
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ret
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disable_irq:; .type disable_irq, %function
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msr daifset, #DAIF_IRQ_BIT
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ret
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disable_fiq:; .type disable_fiq, %function
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msr daifset, #DAIF_FIQ_BIT
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ret
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disable_serror:; .type disable_serror, %function
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msr daifset, #DAIF_ABT_BIT
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ret
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disable_debug_exceptions:
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msr daifset, #DAIF_DBG_BIT
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ret
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read_daif:; .type read_daif, %function
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mrs x0, daif
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ret
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write_daif:; .type write_daif, %function
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msr daif, x0
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ret
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read_spsr:; .type read_spsr, %function
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mrs x0, CurrentEl
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cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
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b.eq read_spsr_el1
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cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
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b.eq read_spsr_el2
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cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
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b.eq read_spsr_el3
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read_spsr_el1:; .type read_spsr_el1, %function
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mrs x0, spsr_el1
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ret
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read_spsr_el2:; .type read_spsr_el2, %function
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mrs x0, spsr_el2
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ret
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read_spsr_el3:; .type read_spsr_el3, %function
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mrs x0, spsr_el3
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ret
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write_spsr:; .type write_spsr, %function
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mrs x1, CurrentEl
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cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
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b.eq write_spsr_el1
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cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
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b.eq write_spsr_el2
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cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
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b.eq write_spsr_el3
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write_spsr_el1:; .type write_spsr_el1, %function
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msr spsr_el1, x0
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isb
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ret
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write_spsr_el2:; .type write_spsr_el2, %function
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msr spsr_el2, x0
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isb
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ret
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write_spsr_el3:; .type write_spsr_el3, %function
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msr spsr_el3, x0
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isb
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ret
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read_elr:; .type read_elr, %function
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mrs x0, CurrentEl
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cmp x0, #(MODE_EL1 << MODE_EL_SHIFT)
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b.eq read_elr_el1
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cmp x0, #(MODE_EL2 << MODE_EL_SHIFT)
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b.eq read_elr_el2
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cmp x0, #(MODE_EL3 << MODE_EL_SHIFT)
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b.eq read_elr_el3
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read_elr_el1:; .type read_elr_el1, %function
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mrs x0, elr_el1
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ret
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read_elr_el2:; .type read_elr_el2, %function
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mrs x0, elr_el2
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ret
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read_elr_el3:; .type read_elr_el3, %function
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mrs x0, elr_el3
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ret
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write_elr:; .type write_elr, %function
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mrs x1, CurrentEl
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cmp x1, #(MODE_EL1 << MODE_EL_SHIFT)
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b.eq write_elr_el1
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cmp x1, #(MODE_EL2 << MODE_EL_SHIFT)
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b.eq write_elr_el2
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cmp x1, #(MODE_EL3 << MODE_EL_SHIFT)
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b.eq write_elr_el3
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write_elr_el1:; .type write_elr_el1, %function
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msr elr_el1, x0
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isb
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ret
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write_elr_el2:; .type write_elr_el2, %function
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msr elr_el2, x0
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isb
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ret
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write_elr_el3:; .type write_elr_el3, %function
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msr elr_el3, x0
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isb
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ret
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dsb:; .type dsb, %function
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dsb sy
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ret
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isb:; .type isb, %function
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isb
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ret
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sev:; .type sev, %function
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sev
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ret
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wfe:; .type wfe, %function
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wfe
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ret
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wfi:; .type wfi, %function
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wfi
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ret
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eret:; .type eret, %function
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eret
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smc:; .type smc, %function
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smc #0
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/* -----------------------------------------------------------------------
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* void zeromem16(void *mem, unsigned int length);
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*
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* Initialise a memory region to 0.
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* The memory address must be 16-byte aligned.
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* -----------------------------------------------------------------------
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*/
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zeromem16:
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add x2, x0, x1
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/* zero 16 bytes at a time */
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z_loop16:
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sub x3, x2, x0
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cmp x3, #16
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b.lt z_loop1
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stp xzr, xzr, [x0], #16
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b z_loop16
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/* zero byte per byte */
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z_loop1:
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cmp x0, x2
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b.eq z_end
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strb wzr, [x0], #1
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b z_loop1
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z_end: ret
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/* --------------------------------------------------------------------------
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* void memcpy16(void *dest, const void *src, unsigned int length)
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*
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* Copy length bytes from memory area src to memory area dest.
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* The memory areas should not overlap.
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* Destination and source addresses must be 16-byte aligned.
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* --------------------------------------------------------------------------
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*/
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memcpy16:
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/* copy 16 bytes at a time */
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m_loop16:
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cmp x2, #16
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b.lt m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, m_end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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m_end: ret
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