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https://github.com/ARM-software/arm-trusted-firmware.git
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4a826ddad8
The runtime exception handling assembler code used magic numbers for saving and restoring the general purpose register context on stack memory. The memory is interpreted as a 'gp_regs' structure and the magic numbers are offsets to members of this structure. This patch replaces the magic number offsets with constants. It also adds compile time assertions to prevent an incorrect assembler view of this structure. Change-Id: Ibf125bfdd62ba3a33e58c5f1d71f8c229720781c
204 lines
4.7 KiB
ArmAsm
204 lines
4.7 KiB
ArmAsm
/*
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* Copyright (c) 2013, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <runtime_svc.h>
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.globl runtime_exceptions
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#include <asm_macros.S>
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.section .text, "ax"; .align 11
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.align 7
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runtime_exceptions:
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x180
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* -----------------------------------------------------
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*/
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sync_exception_sp_el0:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_SP_EL0
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_sp_el0:
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exception_entry save_regs
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mov x0, #IRQ_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_sp_el0:
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exception_entry save_regs
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mov x0, #FIQ_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_sp_el0:
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exception_entry save_regs
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mov x0, #SERROR_SP_EL0
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x380
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_sp_elx:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_SP_ELX
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_sp_elx:
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exception_entry save_regs
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mov x0, #IRQ_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_sp_elx:
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exception_entry save_regs
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mov x0, #FIQ_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_sp_elx:
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exception_entry save_regs
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mov x0, #SERROR_SP_ELX
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x580
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch64:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_AARCH64
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_aarch64:
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exception_entry save_regs
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mov x0, #IRQ_AARCH64
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_aarch64:
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exception_entry save_regs
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mov x0, #FIQ_AARCH64
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_aarch64:
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exception_entry save_regs
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mov x0, #IRQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x780
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* -----------------------------------------------------
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*/
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.align 7
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sync_exception_aarch32:
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exception_entry save_regs
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mov x0, #SYNC_EXCEPTION_AARCH32
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mov x1, sp
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bl sync_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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irq_aarch32:
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exception_entry save_regs
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mov x0, #IRQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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fiq_aarch32:
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exception_entry save_regs
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mov x0, #FIQ_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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serror_aarch32:
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exception_entry save_regs
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mov x0, #SERROR_AARCH32
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mov x1, sp
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bl async_exception_handler
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exception_exit restore_regs
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eret
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.align 7
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