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4a079c752b
Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
146 lines
4.6 KiB
C
146 lines
4.6 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <plat/common/platform.h>
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#include "gxbb_private.h"
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(type == NON_SECURE);
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next_image_info = &bl33_image_ep_info;
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/* None of the images can have 0x0 as the entrypoint. */
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if (next_image_info->pc != 0U) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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struct gxbb_bl31_param {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct gxbb_bl31_param *from_bl2;
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/* Initialize the console to provide early debug support */
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gxbb_console_init();
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/*
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* In debug builds, we pass a special value in 'arg1' to verify platform
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* parameters from BL2 to BL31. In release builds it's not used.
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*/
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assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
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/* Check that params passed from BL2 are not NULL. */
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from_bl2 = (struct gxbb_bl31_param *) arg0;
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/* Check params passed from BL2 are not NULL. */
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* Copy BL33 entry point information. It is stored in Secure RAM, in
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* BL2's address space.
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*/
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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if (bl33_image_ep_info.pc == 0U) {
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ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
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panic();
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}
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}
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void bl31_plat_arch_setup(void)
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{
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gxbb_setup_page_tables();
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enable_mmu_el3(0);
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}
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/*******************************************************************************
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* GICv2 driver setup information
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******************************************************************************/
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static const interrupt_prop_t gxbb_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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static const gicv2_driver_data_t gxbb_gic_data = {
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.gicd_base = GXBB_GICD_BASE,
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.gicc_base = GXBB_GICC_BASE,
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.interrupt_props = gxbb_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
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};
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void bl31_platform_setup(void)
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{
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mhu_secure_init();
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gicv2_driver_init(&gxbb_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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gxbb_thermal_unknown();
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}
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