Lionel Debieve 49abdfd8ce feat(st): disable authentication based on part_number ... STM32MP15xA and STM32MP15xD chip part numbers don't support the secure boot. All functions linked to secure boot must not be used and signed binaries are not allowed on such chip. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I5b85f322f5eb3b64415e1819bd00fb2c99f20695		2022-02-01 13:52:40 +01:00
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allwinner	feat(allwinner): allow to skip PMIC regulator setup	2021-12-27 15:32:22 +00:00
amlogic	Plat AXG: Fix PLAT_MAX_PWR_LVL value	2020-12-29 13:52:11 +00:00
arm	feat(cpu): add library support for Poseidon CPU	2022-01-28 11:12:21 +00:00
brcm	fix: use correct printf format for uint64_t	2021-11-12 13:02:02 +00:00
common	fix: libc: use long for 64-bit types on aarch64	2021-11-08 14:41:17 +00:00
hisilicon	fix: libc: use long for 64-bit types on aarch64	2021-11-08 14:41:17 +00:00
imx	fix(imx8mp): change the BL31 physical load address	2022-01-12 10:33:27 +08:00
intel/soc	plat/intel: do not keep mmc_device_info in stack	2021-04-08 08:44:57 +02:00
marvell	feat(plat/marvell/a3k): add north and south bridge reset registers	2021-12-02 17:37:58 +01:00
mediatek	feat(mt8186): add Vcore DVFS driver	2022-01-13 10:11:39 +08:00
nvidia/tegra	fix: libc: use long for 64-bit types on aarch64	2021-11-08 14:41:17 +00:00
nxp	refactor(ls1028a): fix header file group issue	2022-01-26 10:13:14 +08:00
qemu	feat(plat/qemu): add SPMD support with SPMC at S-EL1	2021-11-29 13:57:57 +01:00
qti	feat(plat/qti/sc7280): add support for pmk7325	2021-10-12 23:51:59 +02:00
renesas	Merge changes I25047322,Id476f815 into integration	2022-01-31 16:53:19 +01:00
rockchip	refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication	2022-01-04 15:26:43 +01:00
rpi	fix: libc: use long for 64-bit types on aarch64	2021-11-08 14:41:17 +00:00
socionext	Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration	2021-12-09 15:03:19 +01:00
st	feat(st): disable authentication based on part_number	2022-02-01 13:52:40 +01:00
ti/k3	plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0	2021-03-26 02:25:44 -05:00
xilinx	feat(versal): add UART1 as console	2021-12-22 03:56:42 -07:00