Varun Wadekar 47d6f5ff16 feat(cpus): workaround for Cortex A78 AE erratum 1941500 ... Cortex A78 AE erratum 1941500 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum is avoided by by setting CPUECTLR_EL1[8] to 1. There is a small performance cost (<0.5%) for setting this bit. SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900 Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2021-08-19 02:15:09 -07:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	feat(cpus): workaround for Cortex A78 AE erratum 1941500	2021-08-19 02:15:09 -07:00
firmware-design.rst	doc: Correct CPACR.FPEN usage	2020-09-14 02:35:50 +00:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	Update cryptographic algorithms in TBBR doc	2020-03-12 17:11:25 +01:00