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https://github.com/ARM-software/arm-trusted-firmware.git
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6197dc98fe
This patch is to restructure system manager. Move platform dependent MACROs to individual platform system manager. Common system manager will remain for those common declaration only. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb
195 lines
8.4 KiB
C
195 lines
8.4 KiB
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_SOCFPGA_SYSTEMMANAGER_H
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#define AGX_SOCFPGA_SYSTEMMANAGER_H
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#include "socfpga_plat_def.h"
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/* System Manager Register Map */
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#define SOCFPGA_SYSMGR_SILICONID_1 0x00
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#define SOCFPGA_SYSMGR_SILICONID_2 0x04
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#define SOCFPGA_SYSMGR_WDDBG 0x08
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#define SOCFPGA_SYSMGR_MPU_STATUS 0x10
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#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C
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#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34
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#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38
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#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C
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#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40
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#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */
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#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */
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#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */
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#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50
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#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54
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#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C
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#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
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#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74
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#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78
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#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C
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#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80
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#define SOCFPGA_SYSMGR_OSC_TRIM 0x84
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#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88
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#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C
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#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90
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#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94
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#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98
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#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C
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#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0
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/* NOC configuration value for Agilex5 */
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#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8
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#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC
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#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0
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#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4
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#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8
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#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC
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#define SOCFPGA_SYSMGR_GPO 0xE4
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#define SOCFPGA_SYSMGR_GPI 0xE8
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#define SOCFPGA_SYSMGR_MPU 0xF0
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#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4
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#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8
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#define SOCFPGA_SYSMGR_DFI_INTF 0xFC
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#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100
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#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104
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#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108
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#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C
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#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110
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#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114
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#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118
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#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C
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#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120
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#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124
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#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128
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#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C
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#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130
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#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134
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#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138
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#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C
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#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140
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#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144
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#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148
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#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C
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#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150
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#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154
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#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158
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#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C
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#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160
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#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164
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#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168
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#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C
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#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170
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#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174
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#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178
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#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C
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#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180
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#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198
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#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C
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#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0
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#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4
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#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8
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#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC
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#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC
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#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0
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#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0
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#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
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#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228
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#define SOCFPGA_SYSMGR_MPFE_status 0x22C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
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#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
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#define DMA0_STREAM_CTRL_REG 0x10D1217C
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#define DMA1_STREAM_CTRL_REG 0x10D12180
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#define SDM_STREAM_CTRL_REG 0x10D12184
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#define USB2_STREAM_CTRL_REG 0x10D12188
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#define USB3_STREAM_CTRL_REG 0x10D1218C
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#define SDMMC_STREAM_CTRL_REG 0x10D12190
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#define NAND_STREAM_CTRL_REG 0x10D12194
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#define ETR_STREAM_CTRL_REG 0x10D12198
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#define TSN0_STREAM_CTRL_REG 0x10D1219C
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#define TSN1_STREAM_CTRL_REG 0x10D121A0
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#define TSN2_STREAM_CTRL_REG 0x10D121A4
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/* Stream ID configuration value for Agilex5 */
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#define TSN0 0x00010001
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#define TSN1 0x00020002
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#define TSN2 0x00030003
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#define NAND 0x00040004
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#define SDMMC 0x00050005
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#define USB0 0x00060006
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#define USB1 0x00070007
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#define DMA0 0x00080008
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#define DMA1 0x00090009
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#define SDM 0x000A000A
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#define CORE_SIGHT_DEBUG 0x000B000B
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/* Field Masking */
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#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
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#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
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#define IDLE_DATA_LWSOC2FPGA BIT(4)
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#define IDLE_DATA_SOC2FPGA BIT(0)
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#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
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#define SYSMGR_ECC_OCRAM_MASK BIT(1)
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#define SYSMGR_ECC_DDR0_MASK BIT(16)
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#define SYSMGR_ECC_DDR1_MASK BIT(17)
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#define WSTREAMIDEN_REG_CTRL BIT(0)
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#define RSTREAMIDEN_REG_CTRL BIT(1)
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#define WMMUSECSID_REG_VAL BIT(4)
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#define RMMUSECSID_REG_VAL BIT(5)
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/* Macros */
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#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
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+ (SOCFPGA_SYSMGR_##_reg))
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#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL | \
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RSTREAMIDEN_REG_CTRL
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#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL | \
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RSTREAMIDEN_REG_CTRL | \
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WMMUSECSID_REG_VAL | RMMUSECSID_REG_VAL
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#endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */
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