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47147013b4
Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
46 lines
1.4 KiB
ReStructuredText
46 lines
1.4 KiB
ReStructuredText
Marvell IO WIN address decoding bindings
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========================================
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IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IO WIN includes a description of the address decoding configuration.
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Transactions that are decoded by CCU windows as IO peripheral, have an additional
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layer of decoding. This additional address decoding layer defines one of the
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following targets:
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- **0x0** = BootRom
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- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
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- **0x2** = SPI direct access
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- **0x3** = PCIe registers
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- **0x4** = MCI Port
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- **0x5** = PCIe port
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Mandatory functions
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-------------------
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- marvell_get_io_win_memory_map
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Returns the IO windows configuration and the number of windows of the
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specific AP.
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Mandatory structures
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--------------------
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- io_win_memory_map
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Array that include the configuration of the windows. Every window/entry is
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a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Example
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-------
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.. code:: c
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struct addr_map_win io_win_memory_map[] = {
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{0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
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{0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
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{0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/
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};
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