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https://github.com/ARM-software/arm-trusted-firmware.git
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46e2c853d6
This is not used in BL31 or Bl32 for this platform. Pass it to BL2_CPPFLAGS instead of defining it for all BL images. This will produce slightly smaller BL31 and Bl32. Change-Id: I66ec5179f8dc5b112e65547335e7dd0a0f4074cd Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#define PLATFORM_STACK_SIZE 0x1000
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT))
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/* topology */
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#define UNIPHIER_MAX_CPUS_PER_CLUSTER U(4)
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#define UNIPHIER_CLUSTER_COUNT U(2)
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#define PLATFORM_CORE_COUNT \
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((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT))
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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#define UNIPHIER_BL2_OFFSET UL(0x00000000)
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#define UNIPHIER_BL2_MAX_SIZE UL(0x00080000)
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/* 0x00080000-0x01000000: reserved for DSP */
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#define UNIPHIER_BL31_OFFSET UL(0x01000000)
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#define UNIPHIER_BL31_MAX_SIZE UL(0x00080000)
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#define UNIPHIER_BL32_OFFSET UL(0x01080000)
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#define UNIPHIER_BL32_MAX_SIZE UL(0x00100000)
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/*
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* The link addresses are determined by UNIPHIER_MEM_BASE + offset.
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* When ENABLE_PIE is set, all the TF images can be loaded anywhere, so
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* UNIPHIER_MEM_BASE is arbitrary.
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*
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* When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that
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* BL2_BASE matches to the physical address where BL2 is loaded, that is,
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* UNIPHIER_MEM_BASE should be the base address of the DRAM region.
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*/
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#define UNIPHIER_MEM_BASE UL(0x00000000)
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#define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET)
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#define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
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#define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET)
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#define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE)
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#define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET)
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#define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 9
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#define MAX_MMAP_REGIONS 13
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#define MAX_IO_HANDLES 2
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#define MAX_IO_DEVICES 2
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define TSP_SEC_MEM_BASE (BL32_BASE)
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#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
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#define TSP_IRQ_SEC_PHY_TIMER 29
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#endif /* PLATFORM_DEF_H */
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