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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
172 lines
5.4 KiB
ArmAsm
172 lines
5.4 KiB
ArmAsm
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a715.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818
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sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20)
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workaround_reset_end cortex_a715, ERRATUM(2331818)
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check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187
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/* GCR_EL1 is only present with FEAT_MTE2. */
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mrs x1, ID_AA64PFR1_EL1
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ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
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cmp x0, #MTE_IMPLEMENTED_ELX
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bne #1f
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sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT
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1:
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/* Mitigation upon ERETAA and ERETAB. */
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mov x0, #2
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msr CORTEX_A715_CPUPSELR_EL3, x0
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isb
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ldr x0, =0xd69f0bff
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msr CORTEX_A715_CPUPOR_EL3, x0
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ldr x0, =0xfffffbff
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msr CORTEX_A715_CPUPMR_EL3, x0
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mov x1, #0
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orr x1, x1, #(1<<0)
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orr x1, x1, #(3<<4)
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orr x1, x1, #(0xf<<6)
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orr x1, x1, #(1<<13)
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orr x1, x1, #(1<<53)
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msr CORTEX_A715_CPUPCR_EL3, x1
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workaround_reset_end cortex_a715, ERRATUM(2344187)
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check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290
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/* Erratum 2413290 workaround is required only if SPE is enabled */
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#if ENABLE_SPE_FOR_NS != 0
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/* Check if Static profiling extension is implemented or present. */
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mrs x1, id_aa64dfr0_el1
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ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
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cbz x0, 1f
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/* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
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sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57)
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sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58)
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1:
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#endif
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workaround_reset_end cortex_a715, ERRATUM(2413290)
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check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947
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sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33)
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workaround_reset_end cortex_a715, ERRATUM(2420947)
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check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384
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sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27)
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workaround_reset_end cortex_a715, ERRATUM(2429384)
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check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
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sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26)
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workaround_reset_end cortex_a715, ERRATUM(2561034)
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check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
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workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106
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mov x0, #3
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msr CORTEX_A715_CPUPSELR_EL3, x0
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isb
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ldr x0, =0xd503339f
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msr CORTEX_A715_CPUPOR_EL3, x0
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ldr x0, =0xfffff3ff
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msr CORTEX_A715_CPUPMR_EL3, x0
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mov x0, #1
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orr x0, x0, #(3<<4)
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orr x0, x0, #(0xf<<6)
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orr x0, x0, #(1<<13)
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orr x0, x0, #(1<<20)
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orr x0, x0, #(1<<22)
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orr x0, x0, #(1<<31)
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orr x0, x0, #(1<<50)
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msr CORTEX_A715_CPUPCR_EL3, x0
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workaround_reset_end cortex_a715, ERRATUM(2728106)
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check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1)
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workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A715 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a715
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a715, CVE(2022, 23960)
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check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a715
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_a715
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a715_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A715_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A715_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a715_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-A715 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a715_regs, "aS"
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cortex_a715_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a715_cpu_reg_dump
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adr x6, cortex_a715_regs
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mrs x8, CORTEX_A715_CPUECTLR_EL1
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ret
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endfunc cortex_a715_cpu_reg_dump
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declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
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cortex_a715_reset_func, \
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cortex_a715_core_pwr_dwn
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