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463b5b4a46
Cortex-A710 erratum 3701772 that applies to all revisions <= r2p1 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775101/latest/ Change-Id: I997c9cfaa75321f22b4f690c4d3f234c0b51c670 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Runtime C routines for errata workarounds and common routines */
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#include <arch.h>
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#include <arch_helpers.h>
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#include <cortex_a75.h>
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#include <cortex_a520.h>
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#include <cortex_a710.h>
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#include <cortex_x4.h>
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#include <lib/cpus/cpu_ops.h>
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#include <lib/cpus/errata.h>
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#if ERRATA_A520_2938996 || ERRATA_X4_2726228
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unsigned int check_if_affected_core(void)
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{
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uint32_t midr_val = read_midr();
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long rev_var = cpu_get_rev_var();
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if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_A520_MIDR)) {
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return check_erratum_cortex_a520_2938996(rev_var);
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} else if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(CORTEX_X4_MIDR)) {
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return check_erratum_cortex_x4_2726228(rev_var);
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}
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return ERRATA_NOT_APPLIES;
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}
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#endif
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#if ERRATA_A75_764081
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bool errata_a75_764081_applies(void)
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{
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long rev_var = cpu_get_rev_var();
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if (check_erratum_cortex_a75_764081(rev_var) == ERRATA_APPLIES) {
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return true;
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}
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return false;
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}
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#endif /* ERRATA_A75_764081 */
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bool errata_ich_vmcr_el2_applies(void)
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{
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switch (EXTRACT_PARTNUM(read_midr())) {
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#if ERRATA_A710_3701772
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case EXTRACT_PARTNUM(CORTEX_A710_MIDR):
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if (check_erratum_cortex_a710_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
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return true;
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break;
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#endif /* ERRATA_A710_3701772 */
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default:
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break;
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}
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return false;
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}
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