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722ca35ecc
On STM32MP15, there is currently an OP-TEE shared memory area at the end of the DDR. But this area will in term be removed. To allow a smooth transition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects the OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default (no behavior change). It will be set to 0 when OP-TEE is aligned, and then later be removed. Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I91146cd8a26a24be22143c212362294c1e880264
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/*
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* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_STM32IMAGE_DEF_H
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#define STM32MP1_STM32IMAGE_DEF_H
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#ifdef AARCH32_SP_OPTEE
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#if STM32MP15_OPTEE_RSV_SHM
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#else
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#define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */
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#endif
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#else
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#define STM32MP_DDR_S_SIZE U(0)
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#define STM32MP_DDR_SHMEM_SIZE U(0)
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#endif
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#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
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#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE
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#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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/* OP-TEE loads from SYSRAM base to BL2 DTB start address */
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#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE
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#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE - STM32MP_DTB_SIZE)
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#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE
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#else /* AARCH32_SP_OPTEE */
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#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */
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#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL32_SIZE)
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#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
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STM32MP_BL2_SIZE)
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#endif /* AARCH32_SP_OPTEE */
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/* DTB initialization value */
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#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_DTB_SIZE)
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL32)
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#define MAX_MMAP_REGIONS 6
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#endif
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/*******************************************************************************
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* STM32MP1 RAW partition offset for MTD devices
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******************************************************************************/
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#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
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#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
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#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
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#endif
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#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
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#ifdef AARCH32_SP_OPTEE
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#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
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#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
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#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
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#endif
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#endif /* STM32MP1_STM32IMAGE_DEF_H */
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