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https://github.com/ARM-software/arm-trusted-firmware.git
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313b776f85
When the Arm(R) Ethos(TM)-N NPU driver is built with TZMP1 support, it will now validate the NPU firmware binary that BL2 is expected to load into the protected memory location specified by ARM_ETHOSN_NPU_IMAGE_BASE. Juno has been updated with a new BL31 memory mapping to allow the SiP service to read the protected memory that contains the NPU firmware binary. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I633256ab7dd4f8f5a6f864c8c98a66bf9dfc37f3
140 lines
3 KiB
C
140 lines
3 KiB
C
/*
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* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/smccc.h>
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#include <platform_def.h>
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#include <services/arm_arch_svc.h>
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#include <plat/arm/common/plat_arm.h>
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/*
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* Table of memory regions for different BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as setup_page_tables() already takes care
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* of mapping it.
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*/
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#ifdef IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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#if TRUSTED_BOARD_BOOT
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/* Map DRAM to authenticate NS_BL2U image. */
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ARM_MAP_NS_DRAM1,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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ARM_MAP_NS_DRAM1,
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#ifdef __aarch64__
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ARM_MAP_DRAM2,
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#endif
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#ifdef SPD_tspd
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ARM_MAP_TSP_SEC_MEM,
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#endif
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#ifdef SPD_opteed
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ARM_MAP_OPTEE_CORE_MEM,
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ARM_OPTEE_PAGEABLE_LOAD_MEM,
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#endif
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#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
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ARM_MAP_BL1_RW,
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#endif
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#ifdef JUNO_ETHOSN_TZMP1
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JUNO_ETHOSN_PROT_FW_RW,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2U
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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CSS_MAP_DEVICE,
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CSS_MAP_SCP_BL2U,
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V2M_MAP_IOFPGA,
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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#ifdef IMAGE_BL31
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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SOC_CSS_MAP_DEVICE,
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ARM_DTB_DRAM_NS,
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#ifdef JUNO_ETHOSN_TZMP1
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JUNO_ETHOSN_PROT_FW_RO,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL32
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const mmap_region_t plat_arm_mmap[] = {
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#ifndef __aarch64__
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ARM_MAP_SHARED_RAM,
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#ifdef PLAT_ARM_MEM_PROT_ADDR
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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#endif
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V2M_MAP_IOFPGA,
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CSS_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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ARM_CASSERT_MMAP
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/*****************************************************************************
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* plat_is_smccc_feature_available() - This function checks whether SMCCC
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* feature is availabile for platform.
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* @fid: SMCCC function id
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*
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* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
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* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
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*****************************************************************************/
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int32_t plat_is_smccc_feature_available(u_register_t fid)
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{
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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return SMC_ARCH_CALL_SUCCESS;
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default:
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return SMC_ARCH_CALL_NOT_SUPPORTED;
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}
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}
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/* Get SOC version */
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int32_t plat_get_soc_version(void)
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{
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return (int32_t)
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(SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
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ARM_SOC_IDENTIFICATION_CODE) |
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(JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
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}
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/* Get SOC revision */
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int32_t plat_get_soc_revision(void)
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{
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unsigned int sys_id;
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sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
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return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
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V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
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}
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