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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
613 lines
17 KiB
ArmAsm
613 lines
17 KiB
ArmAsm
/*
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* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/bl_common.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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.globl smc
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.globl zero_normalmem
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.globl zeromem
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.globl memcpy16
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.globl gpt_tlbi_by_pa_ll
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.globl disable_mmu_el1
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.globl disable_mmu_el3
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.globl disable_mmu_icache_el1
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.globl disable_mmu_icache_el3
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.globl fixup_gdt_reloc
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#if SUPPORT_VFP
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.globl enable_vfp
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#endif
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func smc
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zero_normalmem(void *mem, unsigned int length);
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*
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* Initialise a region in normal memory to 0. This functions complies with the
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* AAPCS and can be called from C code.
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*
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* NOTE: MMU must be enabled when using this function as it can only operate on
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* normal memory. It is intended to be mainly used from C code when MMU
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* is usually enabled.
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* -----------------------------------------------------------------------
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*/
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.equ zero_normalmem, zeromem_dczva
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/* -----------------------------------------------------------------------
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* void zeromem(void *mem, unsigned int length);
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*
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* Initialise a region of device memory to 0. This functions complies with the
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* AAPCS and can be called from C code.
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*
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* NOTE: When data caches and MMU are enabled, zero_normalmem can usually be
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* used instead for faster zeroing.
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*
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* -----------------------------------------------------------------------
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*/
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func zeromem
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/* x2 is the address past the last zeroed address */
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add x2, x0, x1
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/*
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* Uses the fallback path that does not use DC ZVA instruction and
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* therefore does not need enabled MMU
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*/
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b .Lzeromem_dczva_fallback_entry
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endfunc zeromem
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/* -----------------------------------------------------------------------
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* void zeromem_dczva(void *mem, unsigned int length);
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*
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* Fill a region of normal memory of size "length" in bytes with null bytes.
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* MMU must be enabled and the memory be of
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* normal type. This is because this function internally uses the DC ZVA
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* instruction, which generates an Alignment fault if used on any type of
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* Device memory (see section D3.4.9 of the ARMv8 ARM, issue k). When the MMU
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* is disabled, all memory behaves like Device-nGnRnE memory (see section
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* D4.2.8), hence the requirement on the MMU being enabled.
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* NOTE: The code assumes that the block size as defined in DCZID_EL0
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* register is at least 16 bytes.
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*
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* -----------------------------------------------------------------------
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*/
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func zeromem_dczva
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/*
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* The function consists of a series of loops that zero memory one byte
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* at a time, 16 bytes at a time or using the DC ZVA instruction to
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* zero aligned block of bytes, which is assumed to be more than 16.
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* In the case where the DC ZVA instruction cannot be used or if the
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* first 16 bytes loop would overflow, there is fallback path that does
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* not use DC ZVA.
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* Note: The fallback path is also used by the zeromem function that
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* branches to it directly.
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*
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* +---------+ zeromem_dczva
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* | entry |
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* +----+----+
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* |
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* v
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* +---------+
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* | checks |>o-------+ (If any check fails, fallback)
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* +----+----+ |
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* | |---------------+
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* v | Fallback path |
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* +------+------+ |---------------+
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* | 1 byte loop | |
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* +------+------+ .Lzeromem_dczva_initial_1byte_aligned_end
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* | |
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* v |
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* +-------+-------+ |
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* | 16 bytes loop | |
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* +-------+-------+ |
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* | |
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* v |
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* +------+------+ .Lzeromem_dczva_blocksize_aligned
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* | DC ZVA loop | |
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* +------+------+ |
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* +--------+ | |
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* | | | |
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* | v v |
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* | +-------+-------+ .Lzeromem_dczva_final_16bytes_aligned
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* | | 16 bytes loop | |
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* | +-------+-------+ |
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* | | |
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* | v |
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* | +------+------+ .Lzeromem_dczva_final_1byte_aligned
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* | | 1 byte loop | |
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* | +-------------+ |
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* | | |
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* | v |
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* | +---+--+ |
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* | | exit | |
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* | +------+ |
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* | |
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* | +--------------+ +------------------+ zeromem
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* | | +----------------| zeromem function |
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* | | | +------------------+
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* | v v
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* | +-------------+ .Lzeromem_dczva_fallback_entry
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* | | 1 byte loop |
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* | +------+------+
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* | |
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* +-----------+
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*/
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/*
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* Readable names for registers
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*
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* Registers x0, x1 and x2 are also set by zeromem which
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* branches into the fallback path directly, so cursor, length and
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* stop_address should not be retargeted to other registers.
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*/
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cursor .req x0 /* Start address and then current address */
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length .req x1 /* Length in bytes of the region to zero out */
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/* Reusing x1 as length is never used after block_mask is set */
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block_mask .req x1 /* Bitmask of the block size read in DCZID_EL0 */
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stop_address .req x2 /* Address past the last zeroed byte */
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block_size .req x3 /* Size of a block in bytes as read in DCZID_EL0 */
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tmp1 .req x4
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tmp2 .req x5
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#if ENABLE_ASSERTIONS
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/*
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* Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
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* register value and panic if the MMU is disabled.
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*/
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#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
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BL2_RUNS_AT_EL3)
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mrs tmp1, sctlr_el3
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#else
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mrs tmp1, sctlr_el1
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#endif
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tst tmp1, #SCTLR_M_BIT
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ASM_ASSERT(ne)
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#endif /* ENABLE_ASSERTIONS */
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/* stop_address is the address past the last to zero */
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add stop_address, cursor, length
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/*
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* Get block_size = (log2(<block size>) >> 2) (see encoding of
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* dczid_el0 reg)
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*/
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mrs block_size, dczid_el0
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/*
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* Select the 4 lowest bits and convert the extracted log2(<block size
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* in words>) to <block size in bytes>
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*/
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ubfx block_size, block_size, #0, #4
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mov tmp2, #(1 << 2)
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lsl block_size, tmp2, block_size
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#if ENABLE_ASSERTIONS
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/*
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* Assumes block size is at least 16 bytes to avoid manual realignment
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* of the cursor at the end of the DCZVA loop.
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*/
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cmp block_size, #16
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ASM_ASSERT(hs)
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#endif
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/*
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* Not worth doing all the setup for a region less than a block and
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* protects against zeroing a whole block when the area to zero is
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* smaller than that. Also, as it is assumed that the block size is at
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* least 16 bytes, this also protects the initial aligning loops from
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* trying to zero 16 bytes when length is less than 16.
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*/
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cmp length, block_size
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b.lo .Lzeromem_dczva_fallback_entry
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/*
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* Calculate the bitmask of the block alignment. It will never
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* underflow as the block size is between 4 bytes and 2kB.
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* block_mask = block_size - 1
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*/
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sub block_mask, block_size, #1
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/*
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* length alias should not be used after this point unless it is
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* defined as a register other than block_mask's.
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*/
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.unreq length
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/*
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* If the start address is already aligned to zero block size, go
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* straight to the cache zeroing loop. This is safe because at this
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* point, the length cannot be smaller than a block size.
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*/
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tst cursor, block_mask
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b.eq .Lzeromem_dczva_blocksize_aligned
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/*
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* Calculate the first block-size-aligned address. It is assumed that
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* the zero block size is at least 16 bytes. This address is the last
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* address of this initial loop.
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*/
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orr tmp1, cursor, block_mask
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add tmp1, tmp1, #1
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/*
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* If the addition overflows, skip the cache zeroing loops. This is
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* quite unlikely however.
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*/
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cbz tmp1, .Lzeromem_dczva_fallback_entry
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/*
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* If the first block-size-aligned address is past the last address,
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* fallback to the simpler code.
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*/
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cmp tmp1, stop_address
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b.hi .Lzeromem_dczva_fallback_entry
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/*
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* If the start address is already aligned to 16 bytes, skip this loop.
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* It is safe to do this because tmp1 (the stop address of the initial
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* 16 bytes loop) will never be greater than the final stop address.
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*/
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tst cursor, #0xf
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b.eq .Lzeromem_dczva_initial_1byte_aligned_end
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/* Calculate the next address aligned to 16 bytes */
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orr tmp2, cursor, #0xf
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add tmp2, tmp2, #1
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/* If it overflows, fallback to the simple path (unlikely) */
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cbz tmp2, .Lzeromem_dczva_fallback_entry
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/*
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* Next aligned address cannot be after the stop address because the
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* length cannot be smaller than 16 at this point.
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*/
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/* First loop: zero byte per byte */
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1:
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strb wzr, [cursor], #1
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cmp cursor, tmp2
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b.ne 1b
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.Lzeromem_dczva_initial_1byte_aligned_end:
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/*
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* Second loop: we need to zero 16 bytes at a time from cursor to tmp1
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* before being able to use the code that deals with block-size-aligned
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* addresses.
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*/
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cmp cursor, tmp1
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b.hs 2f
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1:
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stp xzr, xzr, [cursor], #16
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cmp cursor, tmp1
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b.lo 1b
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2:
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/*
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* Third loop: zero a block at a time using DC ZVA cache block zeroing
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* instruction.
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*/
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.Lzeromem_dczva_blocksize_aligned:
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/*
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* Calculate the last block-size-aligned address. If the result equals
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* to the start address, the loop will exit immediately.
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*/
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bic tmp1, stop_address, block_mask
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cmp cursor, tmp1
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b.hs 2f
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1:
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/* Zero the block containing the cursor */
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dc zva, cursor
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/* Increment the cursor by the size of a block */
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add cursor, cursor, block_size
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cmp cursor, tmp1
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b.lo 1b
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2:
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/*
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* Fourth loop: zero 16 bytes at a time and then byte per byte the
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* remaining area
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*/
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.Lzeromem_dczva_final_16bytes_aligned:
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/*
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* Calculate the last 16 bytes aligned address. It is assumed that the
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* block size will never be smaller than 16 bytes so that the current
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* cursor is aligned to at least 16 bytes boundary.
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*/
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bic tmp1, stop_address, #15
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cmp cursor, tmp1
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b.hs 2f
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1:
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stp xzr, xzr, [cursor], #16
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cmp cursor, tmp1
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b.lo 1b
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2:
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/* Fifth and final loop: zero byte per byte */
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.Lzeromem_dczva_final_1byte_aligned:
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cmp cursor, stop_address
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b.eq 2f
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1:
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strb wzr, [cursor], #1
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cmp cursor, stop_address
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b.ne 1b
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2:
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ret
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/* Fallback for unaligned start addresses */
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.Lzeromem_dczva_fallback_entry:
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/*
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* If the start address is already aligned to 16 bytes, skip this loop.
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*/
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tst cursor, #0xf
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b.eq .Lzeromem_dczva_final_16bytes_aligned
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/* Calculate the next address aligned to 16 bytes */
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orr tmp1, cursor, #15
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add tmp1, tmp1, #1
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/* If it overflows, fallback to byte per byte zeroing */
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cbz tmp1, .Lzeromem_dczva_final_1byte_aligned
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/* If the next aligned address is after the stop address, fall back */
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cmp tmp1, stop_address
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b.hs .Lzeromem_dczva_final_1byte_aligned
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/* Fallback entry loop: zero byte per byte */
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1:
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strb wzr, [cursor], #1
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cmp cursor, tmp1
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b.ne 1b
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b .Lzeromem_dczva_final_16bytes_aligned
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.unreq cursor
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/*
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* length is already unreq'ed to reuse the register for another
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* variable.
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*/
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.unreq stop_address
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.unreq block_size
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.unreq block_mask
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.unreq tmp1
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.unreq tmp2
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endfunc zeromem_dczva
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/* --------------------------------------------------------------------------
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* void memcpy16(void *dest, const void *src, unsigned int length)
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*
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* Copy length bytes from memory area src to memory area dest.
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* The memory areas should not overlap.
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* Destination and source addresses must be 16-byte aligned.
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* --------------------------------------------------------------------------
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*/
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func memcpy16
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#if ENABLE_ASSERTIONS
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orr x3, x0, x1
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tst x3, #0xf
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ASM_ASSERT(eq)
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#endif
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/* copy 16 bytes at a time */
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m_loop16:
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cmp x2, #16
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b.lo m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, m_end
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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m_end:
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ret
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endfunc memcpy16
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/* ---------------------------------------------------------------------------
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* Disable the MMU at EL3
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* ---------------------------------------------------------------------------
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*/
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func disable_mmu_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu_el3:
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mrs x0, sctlr_el3
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bic x0, x0, x1
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msr sctlr_el3, x0
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isb /* ensure MMU is off */
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dsb sy
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ret
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endfunc disable_mmu_el3
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func disable_mmu_icache_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu_el3
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endfunc disable_mmu_icache_el3
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/* ---------------------------------------------------------------------------
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* Disable the MMU at EL1
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* ---------------------------------------------------------------------------
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*/
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func disable_mmu_el1
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu_el1:
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mrs x0, sctlr_el1
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bic x0, x0, x1
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msr sctlr_el1, x0
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isb /* ensure MMU is off */
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dsb sy
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ret
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endfunc disable_mmu_el1
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func disable_mmu_icache_el1
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu_el1
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endfunc disable_mmu_icache_el1
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/* ---------------------------------------------------------------------------
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* Enable the use of VFP at EL3
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* ---------------------------------------------------------------------------
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*/
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#if SUPPORT_VFP
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func enable_vfp
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mrs x0, cpacr_el1
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orr x0, x0, #CPACR_VFP_BITS
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msr cpacr_el1, x0
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mrs x0, cptr_el3
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mov x1, #AARCH64_CPTR_TFP
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bic x0, x0, x1
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msr cptr_el3, x0
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isb
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ret
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endfunc enable_vfp
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#endif
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/* ---------------------------------------------------------------------------
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* Helper to fixup Global Descriptor table (GDT) and dynamic relocations
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* (.rela.dyn) at runtime.
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*
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* This function is meant to be used when the firmware is compiled with -fpie
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* and linked with -pie options. We rely on the linker script exporting
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* appropriate markers for start and end of the section. For GOT, we
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* expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
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* __RELA_START__ and __RELA_END__.
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*
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* The function takes the limits of the memory to apply fixups to as
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* arguments (which is usually the limits of the relocable BL image).
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* x0 - the start of the fixup region
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* x1 - the limit of the fixup region
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* These addresses have to be 4KB page aligned.
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* ---------------------------------------------------------------------------
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*/
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/* Relocation codes */
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#define R_AARCH64_NONE 0
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#define R_AARCH64_RELATIVE 1027
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func fixup_gdt_reloc
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mov x6, x0
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mov x7, x1
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#if ENABLE_ASSERTIONS
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/* Test if the limits are 4KB aligned */
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orr x0, x0, x1
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|
tst x0, #(PAGE_SIZE_MASK)
|
|
ASM_ASSERT(eq)
|
|
#endif
|
|
/*
|
|
* Calculate the offset based on return address in x30.
|
|
* Assume that this function is called within a page at the start of
|
|
* fixup region.
|
|
*/
|
|
and x2, x30, #~(PAGE_SIZE_MASK)
|
|
subs x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */
|
|
b.eq 3f /* Diff(S) = 0. No relocation needed */
|
|
|
|
adrp x1, __GOT_START__
|
|
add x1, x1, :lo12:__GOT_START__
|
|
adrp x2, __GOT_END__
|
|
add x2, x2, :lo12:__GOT_END__
|
|
|
|
/*
|
|
* GOT is an array of 64_bit addresses which must be fixed up as
|
|
* new_addr = old_addr + Diff(S).
|
|
* The new_addr is the address currently the binary is executing from
|
|
* and old_addr is the address at compile time.
|
|
*/
|
|
1: ldr x3, [x1]
|
|
|
|
/* Skip adding offset if address is < lower limit */
|
|
cmp x3, x6
|
|
b.lo 2f
|
|
|
|
/* Skip adding offset if address is > upper limit */
|
|
cmp x3, x7
|
|
b.hi 2f
|
|
add x3, x3, x0
|
|
str x3, [x1]
|
|
|
|
2: add x1, x1, #8
|
|
cmp x1, x2
|
|
b.lo 1b
|
|
|
|
/* Starting dynamic relocations. Use adrp/adr to get RELA_START and END */
|
|
3: adrp x1, __RELA_START__
|
|
add x1, x1, :lo12:__RELA_START__
|
|
adrp x2, __RELA_END__
|
|
add x2, x2, :lo12:__RELA_END__
|
|
|
|
/*
|
|
* According to ELF-64 specification, the RELA data structure is as
|
|
* follows:
|
|
* typedef struct {
|
|
* Elf64_Addr r_offset;
|
|
* Elf64_Xword r_info;
|
|
* Elf64_Sxword r_addend;
|
|
* } Elf64_Rela;
|
|
*
|
|
* r_offset is address of reference
|
|
* r_info is symbol index and type of relocation (in this case
|
|
* code 1027 which corresponds to R_AARCH64_RELATIVE).
|
|
* r_addend is constant part of expression.
|
|
*
|
|
* Size of Elf64_Rela structure is 24 bytes.
|
|
*/
|
|
|
|
/* Skip R_AARCH64_NONE entry with code 0 */
|
|
1: ldr x3, [x1, #8]
|
|
cbz x3, 2f
|
|
|
|
#if ENABLE_ASSERTIONS
|
|
/* Assert that the relocation type is R_AARCH64_RELATIVE */
|
|
cmp x3, #R_AARCH64_RELATIVE
|
|
ASM_ASSERT(eq)
|
|
#endif
|
|
ldr x3, [x1] /* r_offset */
|
|
add x3, x0, x3
|
|
ldr x4, [x1, #16] /* r_addend */
|
|
|
|
/* Skip adding offset if r_addend is < lower limit */
|
|
cmp x4, x6
|
|
b.lo 2f
|
|
|
|
/* Skip adding offset if r_addend entry is > upper limit */
|
|
cmp x4, x7
|
|
b.hi 2f
|
|
|
|
add x4, x0, x4 /* Diff(S) + r_addend */
|
|
str x4, [x3]
|
|
|
|
2: add x1, x1, #24
|
|
cmp x1, x2
|
|
b.lo 1b
|
|
ret
|
|
endfunc fixup_gdt_reloc
|
|
|
|
/*
|
|
* TODO: Currently only supports size of 4KB,
|
|
* support other sizes as well.
|
|
*/
|
|
func gpt_tlbi_by_pa_ll
|
|
#if ENABLE_ASSERTIONS
|
|
cmp x1, #PAGE_SIZE_4KB
|
|
ASM_ASSERT(eq)
|
|
tst x0, #(PAGE_SIZE_MASK)
|
|
ASM_ASSERT(eq)
|
|
#endif
|
|
lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
|
|
sys #6, c8, c4, #7, x0 /* TLBI RPALOS, <Xt> */
|
|
dsb sy
|
|
ret
|
|
endfunc gpt_tlbi_by_pa_ll
|