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e9ec3cec65
This patch moves the private GIC common accessors from `gic_common.h` to a new private header file `gic_common_private.h`. This patch also adds additional comments to GIC register accessors to highlight the fact that some of them access register values that correspond to multiple interrupt IDs. The convention used is that the `set`, `get` and `clr` accessors access and modify the values corresponding to a single interrupt ID whereas the `read` and `write` GIC register accessors access the raw GIC registers and it could correspond to multiple interrupt IDs depending on the register accessed. Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9
250 lines
8.8 KiB
C
250 lines
8.8 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GICV3_PRIVATE_H__
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#define __GICV3_PRIVATE_H__
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#include <gicv3.h>
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#include <mmio.h>
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#include <stdint.h>
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/*******************************************************************************
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* GICv3 private macro definitions
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******************************************************************************/
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/* Constants to indicate the status of the RWP bit */
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#define RWP_TRUE 1
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#define RWP_FALSE 0
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/*
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* Macro to wait for updates to :
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* GICD_CTLR[2:0] - the Group Enables
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* GICD_CTLR[5:4] - the ARE bits
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* GICD_ICENABLERn - the clearing of enable state for SPIs
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*/
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#define gicd_wait_for_pending_write(gicd_base) \
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do { \
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; \
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} while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
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/*
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* Macro to convert an mpidr to a value suitable for programming into a
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* GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
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* to GICv3.
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*/
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#define gicd_irouter_val_from_mpidr(mpidr, irm) \
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((mpidr & ~(0xff << 24)) | \
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(irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
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/*
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* Macro to wait for updates to :
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* GICR_ICENABLER0
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* GICR_CTLR.DPG1S
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* GICR_CTLR.DPG1NS
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* GICR_CTLR.DPG0
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*/
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#define gicr_wait_for_pending_write(gicr_base) \
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do { \
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; \
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} while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
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/*
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* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
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* are zeroes.
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*/
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#define mpidr_from_gicr_typer(typer_val) \
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((((typer_val >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
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((typer_val >> 32) & 0xffffff))
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/*******************************************************************************
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* Private GICv3 function prototypes for accessing entire registers.
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* Note: The raw register values correspond to multiple interrupt IDs and
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* the number of interrupt IDs involved depends on the register accessed.
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******************************************************************************/
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unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
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unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
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void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
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void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
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/*******************************************************************************
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* Private GICv3 function prototypes for accessing the GIC registers
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* corresponding to a single interrupt ID. These functions use bitwise
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* operations or appropriate register accesses to modify or return
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* the bit-field corresponding the single interrupt ID.
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******************************************************************************/
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unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
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unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id);
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unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id);
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void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_set_igrpmodr0(uintptr_t base, unsigned int id);
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void gicr_set_isenabler0(uintptr_t base, unsigned int id);
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void gicr_set_igroupr0(uintptr_t base, unsigned int id);
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void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
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void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id);
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void gicr_clr_igroupr0(uintptr_t base, unsigned int id);
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void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
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/*******************************************************************************
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* Private GICv3 helper function prototypes
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******************************************************************************/
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void gicv3_spis_configure_defaults(uintptr_t gicd_base);
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void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base);
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void gicv3_secure_spis_configure(uintptr_t gicd_base,
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unsigned int num_ints,
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const unsigned int *sec_intr_list,
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unsigned int int_grp);
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void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
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unsigned int num_ints,
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const unsigned int *sec_intr_list,
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unsigned int int_grp);
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void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
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unsigned int rdistif_num,
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uintptr_t gicr_base,
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mpidr_hash_fn mpidr_to_core_pos);
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void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
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void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
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/*******************************************************************************
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* GIC Distributor interface accessors
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******************************************************************************/
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static inline unsigned int gicd_read_pidr2(uintptr_t base)
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{
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return mmio_read_32(base + GICD_PIDR2_GICV3);
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}
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static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
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{
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return mmio_read_64(base + GICD_IROUTER + (id << 3));
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}
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static inline void gicd_write_irouter(uintptr_t base,
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unsigned int id,
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unsigned long long affinity)
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{
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mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
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}
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static inline void gicd_clr_ctlr(uintptr_t base,
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unsigned int bitmap,
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unsigned int rwp)
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{
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gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
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if (rwp)
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gicd_wait_for_pending_write(base);
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}
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static inline void gicd_set_ctlr(uintptr_t base,
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unsigned int bitmap,
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unsigned int rwp)
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{
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gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
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if (rwp)
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gicd_wait_for_pending_write(base);
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}
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/*******************************************************************************
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* GIC Redistributor interface accessors
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******************************************************************************/
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static inline unsigned long long gicr_read_ctlr(uintptr_t base)
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{
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return mmio_read_64(base + GICR_CTLR);
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}
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static inline unsigned long long gicr_read_typer(uintptr_t base)
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{
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return mmio_read_64(base + GICR_TYPER);
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}
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static inline unsigned int gicr_read_waker(uintptr_t base)
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{
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return mmio_read_32(base + GICR_WAKER);
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}
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static inline void gicr_write_waker(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_WAKER, val);
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}
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/*******************************************************************************
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* GIC Re-distributor functions for accessing entire registers.
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* Note: The raw register values correspond to multiple interrupt IDs and
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* the number of interrupt IDs involved depends on the register accessed.
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******************************************************************************/
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static inline unsigned int gicr_read_icenabler0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ICENABLER0);
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}
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static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICENABLER0, val);
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}
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static inline unsigned int gicr_read_isenabler0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ISENABLER0);
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}
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static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ISENABLER0, val);
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}
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static inline unsigned int gicr_read_igroupr0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_IGROUPR0);
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}
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static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_IGROUPR0, val);
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}
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static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
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{
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return mmio_read_32(base + GICR_IGRPMODR0);
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}
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static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_IGRPMODR0, val);
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}
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static inline unsigned int gicr_read_icfgr1(uintptr_t base)
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{
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return mmio_read_32(base + GICR_ICFGR1);
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}
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static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICR_ICFGR1, val);
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}
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#endif /* __GICV3_PRIVATE_H__ */
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