mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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02462972c9
This patch changes the type of the base address parameter in the ARM device driver APIs to uintptr_t (GIC, CCI, TZC400, PL011). The uintptr_t type allows coverage of the whole memory space and to perform arithmetic operations on the addresses. ARM platform code has also been updated to use uintptr_t as GIC base address in the configuration. Fixes ARM-software/tf-issues#214 Change-Id: I1b87daedadcc8b63e8f113477979675e07d788f1
142 lines
3.9 KiB
C
142 lines
3.9 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <assert.h>
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#include <cci.h>
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#include <debug.h>
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#include <mmio.h>
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#include <stdint.h>
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static uintptr_t g_cci_base;
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static unsigned int g_max_master_id;
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static const int *g_cci_slave_if_map;
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#if DEBUG
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static int validate_cci_map(const int *map)
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{
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unsigned int valid_cci_map = 0;
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int slave_if_id;
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int i;
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/* Validate the map */
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for (i = 0; i <= g_max_master_id; i++) {
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slave_if_id = map[i];
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if (slave_if_id < 0)
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continue;
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if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) {
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tf_printf("Slave interface ID is invalid\n");
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return 0;
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}
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if (valid_cci_map & (1 << slave_if_id)) {
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tf_printf("Multiple masters are assigned same"
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" slave interface ID\n");
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return 0;
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}
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valid_cci_map |= 1 << slave_if_id;
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}
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if (!valid_cci_map) {
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tf_printf("No master is assigned a valid slave interface\n");
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return 0;
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}
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return 1;
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}
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#endif /* DEBUG */
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void cci_init(uintptr_t cci_base,
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const int *map,
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unsigned int num_cci_masters)
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{
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assert(map);
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assert(cci_base);
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g_cci_base = cci_base;
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/*
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* Master Id's are assigned from zero, So in an array of size n
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* the max master id is (n - 1).
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*/
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g_max_master_id = num_cci_masters - 1;
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assert(validate_cci_map(map));
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g_cci_slave_if_map = map;
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}
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void cci_enable_snoop_dvm_reqs(unsigned int master_id)
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{
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int slave_if_id;
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assert(g_cci_base);
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assert(master_id <= g_max_master_id);
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slave_if_id = g_cci_slave_if_map[master_id];
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assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0));
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/*
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* Enable Snoops and DVM messages, no need for Read/Modify/Write as
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* rest of bits are write ignore
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*/
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mmio_write_32(g_cci_base +
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SLAVE_IFACE_OFFSET(slave_if_id) +
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SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT);
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/* Wait for the dust to settle down */
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while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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;
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}
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void cci_disable_snoop_dvm_reqs(unsigned int master_id)
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{
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int slave_if_id;
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assert(g_cci_base);
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assert(master_id <= g_max_master_id);
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slave_if_id = g_cci_slave_if_map[master_id];
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assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0));
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/*
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* Disable Snoops and DVM messages, no need for Read/Modify/Write as
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* rest of bits are write ignore.
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*/
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mmio_write_32(g_cci_base +
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SLAVE_IFACE_OFFSET(slave_if_id) +
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SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT));
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/* Wait for the dust to settle down */
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while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
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;
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}
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