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https://github.com/ARM-software/arm-trusted-firmware.git
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42a293379e
Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
122 lines
3.8 KiB
Makefile
122 lines
3.8 KiB
Makefile
#
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# Copyright (C) 2016 - 2018 Marvell International Ltd.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# https://spdx.org/licenses
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include tools/doimage/doimage.mk
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PLAT_FAMILY := a8k
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PLAT_FAMILY_BASE := plat/marvell/$(PLAT_FAMILY)
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PLAT_INCLUDE_BASE := include/plat/marvell/$(PLAT_FAMILY)
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PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common
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MARVELL_DRV_BASE := drivers/marvell
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MARVELL_COMMON_BASE := plat/marvell/common
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ERRATA_A72_859971 := 1
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# Enable MSS support for a8k family
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MSS_SUPPORT := 1
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# Disable EL3 cache for power management
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BL31_CACHE_DISABLE := 1
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$(eval $(call add_define,BL31_CACHE_DISABLE))
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$(eval $(call add_define,PCI_EP_SUPPORT))
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$(eval $(call assert_boolean,PCI_EP_SUPPORT))
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AP_NUM := 1
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$(eval $(call add_define,AP_NUM))
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DOIMAGEPATH ?= tools/doimage
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DOIMAGETOOL ?= ${DOIMAGEPATH}/doimage
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ROM_BIN_EXT ?= $(BUILD_PLAT)/ble.bin
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DOIMAGE_FLAGS += -b $(ROM_BIN_EXT) $(NAND_DOIMAGE_FLAGS) $(DOIMAGE_SEC_FLAGS)
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# This define specifies DDR type for BLE
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$(eval $(call add_define,CONFIG_DDR4))
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MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v2/gicv2_main.c \
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drivers/arm/gic/v2/gicv2_helpers.c \
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plat/common/plat_gicv2.c
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ATF_INCLUDES := -Iinclude/common/tbbr
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PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
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-I$(PLAT_COMMON_BASE)/include \
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-I$(PLAT_INCLUDE_BASE)/common \
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-Iinclude/drivers/marvell \
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-Iinclude/drivers/marvell/mochi \
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$(ATF_INCLUDES)
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PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
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drivers/console/aarch64/console.S \
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drivers/ti/uart/aarch64/16550_console.S
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BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \
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$(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
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MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c
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BLE_SOURCES := drivers/mentor/i2c/mi2cv.c \
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$(PLAT_COMMON_BASE)/plat_ble_setup.c \
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$(MARVELL_MOCHI_DRV) \
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$(PLAT_COMMON_BASE)/plat_pm.c \
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$(MARVELL_DRV_BASE)/thermal.c \
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$(PLAT_COMMON_BASE)/plat_thermal.c \
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$(BLE_PORTING_SOURCES) \
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$(MARVELL_DRV_BASE)/ccu.c \
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$(MARVELL_DRV_BASE)/io_win.c
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BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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lib/cpus/aarch64/cortex_a72.S
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MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \
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$(MARVELL_DRV_BASE)/iob.c \
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$(MARVELL_DRV_BASE)/mci.c \
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$(MARVELL_DRV_BASE)/amb_adec.c \
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$(MARVELL_DRV_BASE)/ccu.c \
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$(MARVELL_DRV_BASE)/cache_llc.c \
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$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
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$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c
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BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c
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BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
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$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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$(PLAT_COMMON_BASE)/aarch64/plat_arch_config.c \
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$(PLAT_COMMON_BASE)/plat_pm.c \
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$(PLAT_COMMON_BASE)/plat_bl31_setup.c \
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$(MARVELL_COMMON_BASE)/marvell_gicv2.c \
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$(MARVELL_COMMON_BASE)/mrvl_sip_svc.c \
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$(MARVELL_COMMON_BASE)/marvell_ddr_info.c \
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$(BL31_PORTING_SOURCES) \
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$(MARVELL_DRV) \
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$(MARVELL_MOCHI_DRV) \
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$(MARVELL_GIC_SOURCES)
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# Add trace functionality for PM
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BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c
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# Force builds with BL2 image on a80x0 platforms
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ifndef SCP_BL2
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$(error "Error: SCP_BL2 image is mandatory for a8k family")
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endif
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# MSS (SCP) build
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include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
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# BLE (ROM context execution code, AKA binary extension)
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BLE_PATH ?= $(PLAT_COMMON_BASE)/ble
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include ${BLE_PATH}/ble.mk
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$(eval $(call MAKE_BL,e))
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mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL} ${BUILD_PLAT}/ble.bin
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$(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
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$(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
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${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
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