mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-22 20:38:03 +00:00
4156d4daa8
Reword some traces. Use uintptr_t where required. Reduce scope of variables. Improve io_stm32image algo. Complete some IP registers definitions. Add failure on supported DDR (stm32mp1_ddr_init()). Fix cache flush on cache disable (stm32mp1_ddr_setup). Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/*
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* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/st/stm32_gpio.h>
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#include <lib/mmio.h>
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static bool check_gpio(uint32_t bank, uint32_t pin)
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{
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if (pin > GPIO_PIN_MAX) {
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ERROR("%s: wrong pin number (%d)\n", __func__, pin);
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return false;
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}
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if ((bank > GPIO_BANK_K) && (bank != GPIO_BANK_Z)) {
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ERROR("%s: wrong GPIO bank number (%d)\n", __func__, bank);
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return false;
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}
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return true;
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}
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void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
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uint32_t pull, uint32_t alternate)
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{
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uintptr_t base;
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if (!check_gpio(bank, pin)) {
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return;
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}
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if (bank == GPIO_BANK_Z) {
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base = STM32_GPIOZ_BANK;
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} else {
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base = STM32_GPIOA_BANK +
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(bank * STM32_GPIO_BANK_OFFSET);
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}
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mmio_clrbits_32(base + GPIO_MODE_OFFSET,
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((uint32_t)GPIO_MODE_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_MODE_OFFSET,
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(mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
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if ((mode & GPIO_OPEN_DRAIN) != 0U) {
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mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
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} else {
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mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
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}
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mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
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((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
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mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
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((uint32_t)GPIO_PULL_MASK << (pin << 1)));
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mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
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if (pin < GPIO_ALT_LOWER_LIMIT) {
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mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
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mmio_setbits_32(base + GPIO_AFRL_OFFSET,
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alternate << (pin << 2));
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} else {
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mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
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((uint32_t)GPIO_ALTERNATE_MASK <<
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((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
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mmio_setbits_32(base + GPIO_AFRH_OFFSET,
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alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
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2));
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}
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VERBOSE("GPIO %u mode set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_MODE_OFFSET));
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VERBOSE("GPIO %u speed set to 0x%x\n", bank,
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mmio_read_32(base + GPIO_SPEED_OFFSET));
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VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
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mmio_read_32(base + GPIO_PUPD_OFFSET));
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VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
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mmio_read_32(base + GPIO_AFRL_OFFSET));
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VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
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mmio_read_32(base + GPIO_AFRH_OFFSET));
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}
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