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This change creates the following directories under docs/ in order to provide a grouping for the content: - components - design - getting_started - perf - process In each of these directories an index.rst file is created and this serves as an index / landing page for each of the groups when the pages are compiled. Proper layout of the top-level table of contents relies on this directory/index structure. Without this patch it is possible to build the documents correctly with Sphinx but the output looks messy because there is no overall hierarchy. Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
35 lines
1.3 KiB
Text
35 lines
1.3 KiB
Text
Marvell IO WIN address decoding bindings
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=====================================
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IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
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The IO WIN includes a description of the address decoding configuration.
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Transactions that are decoded by CCU windows as IO peripheral, have an additional
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layer of decoding. This additional address decoding layer defines one of the
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following targets:
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0x0 = BootRom
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0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
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0x2 = SPI direct access
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0x3 = PCIe registers
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0x4 = MCI Port
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0x5 = PCIe port
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Mandatory functions:
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- marvell_get_io_win_memory_map
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returns the IO windows configuration and the number of windows
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of the specific AP.
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Mandatory structures:
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io_win_memory_map - Array that include the configuration of the windows
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every window/entry is a struct which has 3 parameters:
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- Base address of the window
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- Size of the window
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- Target-ID of the window
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Example:
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struct addr_map_win io_win_memory_map[] = {
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{0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
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{0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
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{0x00000000f6000000, 0x000000000100000, MCIPHY_TID}, /* MCI window 1Mb for PHY-reg*/
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};
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