arm-trusted-firmware/lib/cpus/aarch64/cpuamu.c
Daniel Boulby 4069292388 Fix MISRA Rule 5.7 Part 1
Rule 5.7: A tag name shall be a unique identifier

There were 2 amu_ctx struct type definitions:
    - In lib/extensions/amu/aarch64/amu.c
    - In lib/cpus/aarch64/cpuamu.c

Renamed the latter to cpuamu_ctx to avoid this name clash

To avoid violation of Rule 8.3 also change name of function
amu_ctxs to unique name (cpuamu_ctxs) since it now returns a
different type (cpuamu_ctx) than the other amu_ctxs function

Fixed for:
    make LOG_LEVEL=50 PLAT=fvp

Change-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-06-12 13:21:36 +01:00

70 lines
1.5 KiB
C

/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cpuamu.h>
#include <platform.h>
#include <pubsub_events.h>
#define CPUAMU_NR_COUNTERS 5U
struct cpuamu_ctx {
uint64_t cnts[CPUAMU_NR_COUNTERS];
unsigned int mask;
};
static struct cpuamu_ctx cpuamu_ctxs[PLATFORM_CORE_COUNT];
int midr_match(unsigned int cpu_midr)
{
unsigned int midr, midr_mask;
midr = (unsigned int)read_midr();
midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
(MIDR_PN_MASK << MIDR_PN_SHIFT);
return ((midr & midr_mask) == (cpu_midr & midr_mask));
}
void cpuamu_context_save(unsigned int nr_counters)
{
struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
unsigned int i;
assert(nr_counters <= CPUAMU_NR_COUNTERS);
/* Save counter configuration */
ctx->mask = cpuamu_read_cpuamcntenset_el0();
/* Disable counters */
cpuamu_write_cpuamcntenclr_el0(ctx->mask);
isb();
/* Save counters */
for (i = 0; i < nr_counters; i++)
ctx->cnts[i] = cpuamu_cnt_read(i);
}
void cpuamu_context_restore(unsigned int nr_counters)
{
struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
unsigned int i;
assert(nr_counters <= CPUAMU_NR_COUNTERS);
/*
* Disable counters. They were enabled early in the
* CPU reset function.
*/
cpuamu_write_cpuamcntenclr_el0(ctx->mask);
isb();
/* Restore counters */
for (i = 0; i < nr_counters; i++)
cpuamu_cnt_write(i, ctx->cnts[i]);
isb();
/* Restore counter configuration */
cpuamu_write_cpuamcntenset_el0(ctx->mask);
}