mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-22 20:38:03 +00:00
402b3cf876
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/*
|
|
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <platform_def.h>
|
|
#include <plat/arm/common/plat_arm.h>
|
|
|
|
/*
|
|
* Table of memory regions for different BL stages to map using the MMU.
|
|
* This doesn't include Trusted SRAM as setup_page_tables() already takes care
|
|
* of mapping it.
|
|
*/
|
|
#ifdef IMAGE_BL1
|
|
const mmap_region_t plat_arm_mmap[] = {
|
|
ARM_MAP_SHARED_RAM,
|
|
V2M_MAP_FLASH0_RW,
|
|
V2M_MAP_IOFPGA,
|
|
CSS_MAP_DEVICE,
|
|
SOC_CSS_MAP_DEVICE,
|
|
#if TRUSTED_BOARD_BOOT
|
|
/* Map DRAM to authenticate NS_BL2U image. */
|
|
ARM_MAP_NS_DRAM1,
|
|
#endif
|
|
{0}
|
|
};
|
|
#endif
|
|
#ifdef IMAGE_BL2
|
|
const mmap_region_t plat_arm_mmap[] = {
|
|
ARM_MAP_SHARED_RAM,
|
|
V2M_MAP_FLASH0_RW,
|
|
#ifdef PLAT_ARM_MEM_PROT_ADDR
|
|
ARM_V2M_MAP_MEM_PROTECT,
|
|
#endif
|
|
V2M_MAP_IOFPGA,
|
|
CSS_MAP_DEVICE,
|
|
SOC_CSS_MAP_DEVICE,
|
|
ARM_MAP_NS_DRAM1,
|
|
#ifdef __aarch64__
|
|
ARM_MAP_DRAM2,
|
|
#endif
|
|
#ifdef SPD_tspd
|
|
ARM_MAP_TSP_SEC_MEM,
|
|
#endif
|
|
#ifdef SPD_opteed
|
|
ARM_MAP_OPTEE_CORE_MEM,
|
|
ARM_OPTEE_PAGEABLE_LOAD_MEM,
|
|
#endif
|
|
{0}
|
|
};
|
|
#endif
|
|
#ifdef IMAGE_BL2U
|
|
const mmap_region_t plat_arm_mmap[] = {
|
|
ARM_MAP_SHARED_RAM,
|
|
CSS_MAP_DEVICE,
|
|
CSS_MAP_SCP_BL2U,
|
|
V2M_MAP_IOFPGA,
|
|
SOC_CSS_MAP_DEVICE,
|
|
{0}
|
|
};
|
|
#endif
|
|
#ifdef IMAGE_BL31
|
|
const mmap_region_t plat_arm_mmap[] = {
|
|
ARM_MAP_SHARED_RAM,
|
|
V2M_MAP_IOFPGA,
|
|
CSS_MAP_DEVICE,
|
|
#ifdef PLAT_ARM_MEM_PROT_ADDR
|
|
ARM_V2M_MAP_MEM_PROTECT,
|
|
#endif
|
|
SOC_CSS_MAP_DEVICE,
|
|
{0}
|
|
};
|
|
#endif
|
|
#ifdef IMAGE_BL32
|
|
const mmap_region_t plat_arm_mmap[] = {
|
|
#ifndef __aarch64__
|
|
ARM_MAP_SHARED_RAM,
|
|
#ifdef PLAT_ARM_MEM_PROT_ADDR
|
|
ARM_V2M_MAP_MEM_PROTECT,
|
|
#endif
|
|
#endif
|
|
V2M_MAP_IOFPGA,
|
|
CSS_MAP_DEVICE,
|
|
SOC_CSS_MAP_DEVICE,
|
|
{0}
|
|
};
|
|
#endif
|
|
|
|
ARM_CASSERT_MMAP
|