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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
55 lines
1.4 KiB
ArmAsm
55 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <nevis.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_func_start nevis
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/* ----------------------------------------------------
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* Disable speculative loads
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* ----------------------------------------------------
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*/
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msr SSBS, xzr
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cpu_reset_func_end nevis
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func nevis_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \
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NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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isb
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ret
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endfunc nevis_core_pwr_dwn
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.section .rodata.nevis_regs, "aS"
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nevis_regs: /* The ASCII list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func nevis_cpu_reg_dump
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adr x6, nevis_regs
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mrs x8, NEVIS_CPUECTLR_EL1
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ret
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endfunc nevis_cpu_reg_dump
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declare_cpu_ops nevis, NEVIS_MIDR, \
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nevis_reset_func, \
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nevis_core_pwr_dwn
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