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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
288 lines
9 KiB
ArmAsm
288 lines
9 KiB
ArmAsm
/*
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* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v1.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
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/* Inserts a DMB SY before and after MRS PAR_EL1 */
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ldr x0, =0x0
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msr NEOVERSE_V1_CPUPSELR_EL3, x0
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ldr x0, = 0xEE070F14
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msr NEOVERSE_V1_CPUPOR_EL3, x0
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ldr x0, = 0xFFFF0FFF
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msr NEOVERSE_V1_CPUPMR_EL3, x0
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ldr x0, =0x4005027FF
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msr NEOVERSE_V1_CPUPCR_EL3, x0
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/* Inserts a DMB SY before STREX imm offset */
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ldr x0, =0x1
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msr NEOVERSE_V1_CPUPSELR_EL3, x0
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ldr x0, =0x00e8400000
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msr NEOVERSE_V1_CPUPOR_EL3, x0
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ldr x0, =0x00fff00000
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msr NEOVERSE_V1_CPUPMR_EL3, x0
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ldr x0, = 0x4001027FF
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msr NEOVERSE_V1_CPUPCR_EL3, x0
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/* Inserts a DMB SY before STREX[BHD}/STLEX* */
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ldr x0, =0x2
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msr NEOVERSE_V1_CPUPSELR_EL3, x0
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ldr x0, =0x00e8c00040
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msr NEOVERSE_V1_CPUPOR_EL3, x0
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ldr x0, =0x00fff00040
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msr NEOVERSE_V1_CPUPMR_EL3, x0
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ldr x0, = 0x4001027FF
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msr NEOVERSE_V1_CPUPCR_EL3, x0
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/* Inserts a DMB SY after STREX imm offset */
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ldr x0, =0x3
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msr NEOVERSE_V1_CPUPSELR_EL3, x0
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ldr x0, =0x00e8400000
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msr NEOVERSE_V1_CPUPOR_EL3, x0
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ldr x0, =0x00fff00000
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msr NEOVERSE_V1_CPUPMR_EL3, x0
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ldr x0, = 0x4004027FF
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msr NEOVERSE_V1_CPUPCR_EL3, x0
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/* Inserts a DMB SY after STREX[BHD}/STLEX* */
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ldr x0, =0x4
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msr NEOVERSE_V1_CPUPSELR_EL3, x0
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ldr x0, =0x00e8c00040
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msr NEOVERSE_V1_CPUPOR_EL3, x0
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ldr x0, =0x00fff00040
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msr NEOVERSE_V1_CPUPMR_EL3, x0
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ldr x0, = 0x4004027FF
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msr NEOVERSE_V1_CPUPCR_EL3, x0
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workaround_reset_end neoverse_v1, ERRATUM(1618635)
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check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
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workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
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/* Set bit 53 in CPUECTLR_EL1 */
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sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
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workaround_reset_end neoverse_v1, ERRATUM(1774420)
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check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
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workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
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/* Set bit 2 in ACTLR2_EL1 */
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sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
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workaround_reset_end neoverse_v1, ERRATUM(1791573)
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check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
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workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
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/* Set bit 28 in ACTLR2_EL1 */
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sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
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workaround_reset_end neoverse_v1, ERRATUM(1852267)
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check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
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workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
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/* Set bit 8 in CPUECTLR_EL1 */
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sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
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workaround_reset_end neoverse_v1, ERRATUM(1925756)
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check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
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mov x0, #0
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3900002
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #1
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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mov x0, #2
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msr S3_6_C15_C8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_C15_C8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_C15_C8_1, x0
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workaround_reset_end neoverse_v1, ERRATUM(1940577)
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check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
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mov x0, #0x3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0xEE010F12
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msr S3_6_C15_C8_2, x0
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ldr x0, =0xFFFF0FFF
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x80000000003FF
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msr S3_6_C15_C8_1, x0
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workaround_reset_end neoverse_v1, ERRATUM(1966096)
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check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
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mrs x1, NEOVERSE_V1_CPUECTLR_EL1
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mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
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bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
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msr NEOVERSE_V1_CPUECTLR_EL1, x1
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workaround_reset_end neoverse_v1, ERRATUM(2108267)
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check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2)
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workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
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mov x0, #0x3
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msr S3_6_C15_C8_0, x0
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ldr x0, =0xEE720F14
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msr S3_6_C15_C8_2, x0
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ldr x0, =0xFFFF0FDF
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msr S3_6_C15_C8_3, x0
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ldr x0, =0x40000005003FF
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msr S3_6_C15_C8_1, x0
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workaround_reset_end neoverse_v1, ERRATUM(2139242)
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check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
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ldr x0, =0x5
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msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
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workaround_reset_end neoverse_v1, ERRATUM(2216392)
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check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
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/* Set bit 0 in ACTLR2_EL1 */
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sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
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workaround_reset_end neoverse_v1, ERRATUM(2294912)
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check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2)
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workaround_runtime_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377
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/* Set bit 61 in CPUACTLR5_EL1 */
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sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61
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workaround_runtime_end neoverse_v1, ERRATUM(2348377)
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check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1)
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workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
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/* Set bit 40 in ACTLR2_EL1 */
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sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
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workaround_reset_end neoverse_v1, ERRATUM(2372203)
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check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
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workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_v1, ERRATUM(2743093)
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check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
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workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
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sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
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sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
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workaround_reset_end neoverse_v1, ERRATUM(2743233)
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check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
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workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
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sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
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workaround_reset_end neoverse_v1, ERRATUM(2779461)
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check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
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workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-V1 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v1
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v1, CVE(2022,23960)
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check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_v1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
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isb
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ret
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endfunc neoverse_v1_core_pwr_dwn
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cpu_reset_func_start neoverse_v1
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_v1
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/* ---------------------------------------------
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* This function provides Neoverse-V1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v1_regs, "aS"
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neoverse_v1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v1_cpu_reg_dump
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adr x6, neoverse_v1_regs
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mrs x8, NEOVERSE_V1_CPUECTLR_EL1
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ret
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endfunc neoverse_v1_cpu_reg_dump
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declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \
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neoverse_v1_reset_func, \
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neoverse_v1_core_pwr_dwn
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