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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
162 lines
5.8 KiB
ArmAsm
162 lines
5.8 KiB
ArmAsm
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78c.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
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/* Disable allocation of splintered pages in the L2 TLB */
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sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
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workaround_reset_end cortex_a78c, ERRATUM(1827430)
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check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0)
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workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440
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/* Force Atomic Store to WB memory be done in L1 data cache */
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sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2)
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workaround_reset_end cortex_a78c, ERRATUM(1827440)
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check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
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workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
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/* --------------------------------------------------------
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* Place the data prefetcher in the most conservative mode
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* to reduce prefetches by writing the following bits to
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* the value indicated: ecltr[7:6], PF_MODE = 2'b11
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* --------------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
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workaround_reset_end cortex_a78c, ERRATUM(2132064)
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check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
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ldr x0, =0x5
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msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
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ldr x0, =0x10F600E000
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msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
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ldr x0, =0x10FF80E000
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msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
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ldr x0, =0x80000000003FF
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msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
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workaround_reset_end cortex_a78c, ERRATUM(2242638)
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check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749
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sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0
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workaround_reset_end cortex_a78c, ERRATUM(2376749)
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check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411
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sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40
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workaround_reset_end cortex_a78c, ERRATUM(2395411)
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check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027
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ldr x0, =0x3
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msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xEE010F10
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msr CORTEX_A78C_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFF1F0FFE
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msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
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ldr x0, =0x100000004003FF
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msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
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workaround_reset_end cortex_a78c, ERRATUM(2683027)
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check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55)
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sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56)
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workaround_reset_end cortex_a78c, ERRATUM(2743232)
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check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2)
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workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_a78c, ERRATUM(2772121)
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check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2)
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workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484
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sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_a78c, ERRATUM(2779484)
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check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2)
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check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A78c generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a78c
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78c, CVE(2022, 23960)
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cpu_reset_func_start cortex_a78c
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cpu_reset_func_end cortex_a78c
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a78c_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
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isb
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ret
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endfunc cortex_a78c_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a78c specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78c_regs, "aS"
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cortex_a78c_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78c_cpu_reg_dump
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adr x6, cortex_a78c_regs
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mrs x8, CORTEX_A78C_CPUECTLR_EL1
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ret
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endfunc cortex_a78c_cpu_reg_dump
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declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
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cortex_a78c_reset_func, \
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cortex_a78c_core_pwr_dwn
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