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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
61 lines
1.4 KiB
ArmAsm
61 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2019-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a65.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if !HW_ASSISTED_COHERENCY
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#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS
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#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A65.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a65_reset_func
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mov x19, x30
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#if ERRATA_DSU_936184
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bl errata_dsu_936184_wa
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#endif
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ret x19
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endfunc cortex_a65_reset_func
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func cortex_a65_cpu_pwr_dwn
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mrs x0, CORTEX_A65_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A65_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a65_cpu_pwr_dwn
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.section .rodata.cortex_a65_regs, "aS"
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cortex_a65_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a65_cpu_reg_dump
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adr x6, cortex_a65_regs
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mrs x8, CORTEX_A65_ECTLR_EL1
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ret
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endfunc cortex_a65_cpu_reg_dump
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declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \
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cortex_a65_reset_func, \
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cortex_a65_cpu_pwr_dwn
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