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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
233 lines
8.1 KiB
ArmAsm
233 lines
8.1 KiB
ArmAsm
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a510.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
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/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
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sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
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CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH
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workaround_reset_end cortex_a510, ERRATUM(1922240)
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check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
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workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
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/* Apply workaround */
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mov x0, xzr
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msr S3_6_C15_C4_0, x0
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isb
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mov x0, #0x8500000
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msr S3_6_C15_C4_2, x0
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mov x0, #0x1F700000
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movk x0, #0x8, lsl #32
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msr S3_6_C15_C4_3, x0
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mov x0, #0x3F1
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movk x0, #0x110, lsl #16
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msr S3_6_C15_C4_1, x0
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workaround_reset_end cortex_a510, ERRATUM(2041909)
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check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
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workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
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/* Apply the workaround by disabling ReadPreferUnique. */
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sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \
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CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH
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workaround_reset_end cortex_a510, ERRATUM(2042739)
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check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
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workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326
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/* Apply workaround */
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mov x0, #1
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msr S3_6_C15_C4_0, x0
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isb
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mov x0, #0x0100
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movk x0, #0x0E08, lsl #16
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msr S3_6_C15_C4_2, x0
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mov x0, #0x0300
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movk x0, #0x0F1F, lsl #16
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movk x0, #0x0008, lsl #32
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msr S3_6_C15_C4_3, x0
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mov x0, #0x03F1
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movk x0, #0x00C0, lsl #16
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msr S3_6_C15_C4_1, x0
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isb
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workaround_reset_end cortex_a510, ERRATUM(2080326)
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check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2)
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workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
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/*
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* Force L2 allocation of transient lines by setting
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* CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
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*/
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #1
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
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msr CORTEX_A510_CPUECTLR_EL1, x0
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workaround_reset_end cortex_a510, ERRATUM(2172148)
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check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
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workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
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/* Set bit 18 in CPUACTLR_EL1 */
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sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
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CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH
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/* Set bit 25 in CMPXACTLR_EL1 */
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sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
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CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH
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workaround_reset_end cortex_a510, ERRATUM(2218950)
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check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
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/* --------------------------------------------------
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* This workaround is not a typical errata fix. MPMM
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* is disabled here, but this conflicts with the BL31
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* MPMM support. So in addition to simply disabling
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* the feature, a flag is set in the MPMM library
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* indicating that it should not be enabled even if
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* ENABLE_MPMM=1.
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* --------------------------------------------------
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*/
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workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
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/* Disable MPMM */
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mrs x0, CPUMPMMCR_EL3
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bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
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msr CPUMPMMCR_EL3, x0
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#if ENABLE_MPMM && IMAGE_BL31
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/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
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bl mpmm_errata_disable
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#endif
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workaround_reset_end cortex_a510, ERRATUM(2250311)
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check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
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workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
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/* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
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sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \
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CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH
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workaround_reset_end cortex_a510, ERRATUM(2288014)
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check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
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workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
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/*
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* Set CPUACTLR_EL1[17] to 1'b1, which disables
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* specific microarchitectural clock gating
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* behaviour.
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*/
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sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17
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workaround_reset_end cortex_a510, ERRATUM(2347730)
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check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
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workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
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/*
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* Cacheable atomic operations can be forced
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* to be executed near by setting
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* IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found
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* in [40:38] of CPUECTLR_EL1.
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*/
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sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \
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CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH
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workaround_reset_end cortex_a510, ERRATUM(2371937)
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check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
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workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
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sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38
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workaround_reset_end cortex_a510, ERRATUM(2666669)
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check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
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.global erratum_cortex_a510_2684597_wa
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workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
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/*
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* Many assemblers do not yet understand the "tsb csync" mnemonic,
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* so use the equivalent hint instruction.
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*/
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hint #18 /* tsb csync */
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workaround_runtime_end cortex_a510, ERRATUM(2684597)
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check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
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/*
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* ERRATA_DSU_2313941 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a510
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
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.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
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add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a510_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_a510_core_pwr_dwn
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cpu_reset_func_start cortex_a510
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_a510
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/* ---------------------------------------------
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* This function provides Cortex-A510 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a510_regs, "aS"
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cortex_a510_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a510_cpu_reg_dump
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adr x6, cortex_a510_regs
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mrs x8, CORTEX_A510_CPUECTLR_EL1
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ret
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endfunc cortex_a510_cpu_reg_dump
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declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
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cortex_a510_reset_func, \
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cortex_a510_core_pwr_dwn
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