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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
136 lines
3.7 KiB
ArmAsm
136 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a35.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a35_disable_dcache
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sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
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isb
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ret
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endfunc cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a35_disable_smp
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sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
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isb
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dsb sy
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ret
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endfunc cortex_a35_disable_smp
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workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
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sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
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workaround_reset_end cortex_a35, ERRATUM(855472)
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check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A35.
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* -------------------------------------------------
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*/
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cpu_reset_func_start cortex_a35
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
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cpu_reset_func_end cortex_a35
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func cortex_a35_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a35_disable_smp
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endfunc cortex_a35_core_pwr_dwn
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func cortex_a35_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a35_disable_smp
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endfunc cortex_a35_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a35 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a35_regs, "aS"
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cortex_a35_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a35_cpu_reg_dump
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adr x6, cortex_a35_regs
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mrs x8, CORTEX_A35_CPUECTLR_EL1
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ret
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endfunc cortex_a35_cpu_reg_dump
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declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \
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cortex_a35_reset_func, \
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cortex_a35_core_pwr_dwn, \
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cortex_a35_cluster_pwr_dwn
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