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https://github.com/ARM-software/arm-trusted-firmware.git
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3fb52e41fd
Errata printing is done directly via generic_errata_report. This commit removes the unused \_cpu\()_errata_report functions for all cores, and removes errata_func from cpu_ops. Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c Signed-off-by: Ryan Everett <ryan.everett@arm.com>
172 lines
3.5 KiB
ArmAsm
172 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a17.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a17_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A17_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a17_disable_smp
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func cortex_a17_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A17_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a17_enable_smp
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A17 Errata #852421.
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* This applies only to revision <= r1p2 of Cortex A17.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ----------------------------------------------------
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*/
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func errata_a17_852421_wa
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_852421
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A17_IMP_DEF_REG1
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orr r0, r0, #(1<<24)
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stcopr r0, CORTEX_A17_IMP_DEF_REG1
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1:
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bx r2
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endfunc errata_a17_852421_wa
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func check_errata_852421
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_852421
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add_erratum_entry cortex_a17, ERRATUM(852421), ERRATA_A17_852421
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/* ----------------------------------------------------
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* Errata Workaround for Cortex A17 Errata #852423.
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* This applies only to revision <= r1p2 of Cortex A17.
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* Inputs:
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* r0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: r0-r3
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* ----------------------------------------------------
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*/
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func errata_a17_852423_wa
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/*
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* Compare r0 against revision r1p2
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*/
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mov r2, lr
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bl check_errata_852423
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cmp r0, #ERRATA_NOT_APPLIES
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beq 1f
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ldcopr r0, CORTEX_A17_IMP_DEF_REG1
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orr r0, r0, #(1<<12)
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stcopr r0, CORTEX_A17_IMP_DEF_REG1
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1:
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bx r2
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endfunc errata_a17_852423_wa
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func check_errata_852423
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mov r1, #0x12
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b cpu_rev_var_ls
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endfunc check_errata_852423
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add_erratum_entry cortex_a17, ERRATUM(852423), ERRATA_A17_852423
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func check_errata_cve_2017_5715
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#if WORKAROUND_CVE_2017_5715
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mov r0, #ERRATA_APPLIES
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#else
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mov r0, #ERRATA_MISSING
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#endif
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bx lr
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endfunc check_errata_cve_2017_5715
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add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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func cortex_a17_reset_func
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mov r5, lr
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bl cpu_get_rev_var
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mov r4, r0
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#if ERRATA_A17_852421
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mov r0, r4
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bl errata_a17_852421_wa
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#endif
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#if ERRATA_A17_852423
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mov r0, r4
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bl errata_a17_852423_wa
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#endif
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#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
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ldr r0, =wa_cve_2017_5715_bpiall_vbar
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stcopr r0, VBAR
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stcopr r0, MVBAR
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/* isb will be applied in the course of the reset func */
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#endif
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mov lr, r5
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b cortex_a17_enable_smp
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endfunc cortex_a17_reset_func
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func cortex_a17_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a17_disable_smp
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endfunc cortex_a17_core_pwr_dwn
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func cortex_a17_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Flush L2 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a17_disable_smp
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endfunc cortex_a17_cluster_pwr_dwn
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declare_cpu_ops cortex_a17, CORTEX_A17_MIDR, \
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cortex_a17_reset_func, \
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cortex_a17_core_pwr_dwn, \
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cortex_a17_cluster_pwr_dwn
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