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https://github.com/ARM-software/arm-trusted-firmware.git
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3fabca724a
`r3` is used to pass the base address of the transfer list. Make sure we update the context structure with this register value so it is populated with this information prior to executing the next stage. Change-Id: Ie1eedbd2eb68b592df30779625691e8975d987bf Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
267 lines
9 KiB
C
267 lines
9 KiB
C
/*
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* Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/build_message.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <drivers/console.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/pmf/pmf.h>
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#include <lib/psci/psci.h>
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#include <lib/runtime_instr.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include <platform_sp_min.h>
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#include <services/std_svc.h>
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#include <smccc_helpers.h>
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#include "sp_min_private.h"
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#if ENABLE_RUNTIME_INSTRUMENTATION
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PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
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RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
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#endif
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/* Pointers to per-core cpu contexts */
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static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
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/* SP_MIN only stores the non secure smc context */
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static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
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/******************************************************************************
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* Define the smccc helper library APIs
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*****************************************************************************/
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void *smc_get_ctx(unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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return &sp_min_smc_context[plat_my_core_pos()];
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}
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void smc_set_next_ctx(unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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/* SP_MIN stores only non secure smc context. Nothing to do here */
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}
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void *smc_get_next_ctx(void)
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{
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return &sp_min_smc_context[plat_my_core_pos()];
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}
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* for the calling CPU that was set as the context for the specified security
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* state. NULL is returned if no such structure has been specified.
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******************************************************************************/
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void *cm_get_context(uint32_t security_state)
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{
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assert(security_state == NON_SECURE);
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return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state for the calling CPU
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******************************************************************************/
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(security_state == NON_SECURE);
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sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
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}
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* for the CPU identified by `cpu_idx` that was set as the context for the
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* specified security state. NULL is returned if no such structure has been
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* specified.
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******************************************************************************/
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void *cm_get_context_by_index(unsigned int cpu_idx,
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unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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return sp_min_cpu_ctx_ptr[cpu_idx];
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state for the CPU identified by CPU index.
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******************************************************************************/
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void cm_set_context_by_index(unsigned int cpu_idx, void *context,
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unsigned int security_state)
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{
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assert(security_state == NON_SECURE);
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sp_min_cpu_ctx_ptr[cpu_idx] = context;
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}
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static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
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smc_ctx_t *next_smc_ctx)
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{
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next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
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next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
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next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
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next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
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next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
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next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
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next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
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}
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/*******************************************************************************
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* This function invokes the PSCI library interface to initialize the
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* non secure cpu context and copies the relevant cpu context register values
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* to smc context. These registers will get programmed during `smc_exit`.
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******************************************************************************/
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static void sp_min_prepare_next_image_entry(void)
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{
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entry_point_info_t *next_image_info;
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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u_register_t ns_sctlr;
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/* Program system registers to proceed to non-secure */
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next_image_info = sp_min_plat_get_bl33_ep_info();
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assert(next_image_info);
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assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
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INFO("SP_MIN: Preparing exit to normal world\n");
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print_entry_point_info(next_image_info);
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psci_prepare_next_non_secure_ctx(next_image_info);
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smc_set_next_ctx(NON_SECURE);
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/* Copy r0, lr and spsr from cpu context to SMC context */
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copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
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smc_get_next_ctx());
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/* Temporarily set the NS bit to access NS SCTLR */
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
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write_sctlr(ns_sctlr);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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}
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/******************************************************************************
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* Implement the ARM Standard Service function to get arguments for a
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* particular service.
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*****************************************************************************/
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uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
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{
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/* Setup the arguments for PSCI Library */
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DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
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/* PSCI is the only ARM Standard Service implemented */
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assert(svc_mask == PSCI_FID_MASK);
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return (uintptr_t)&psci_args;
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}
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/******************************************************************************
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* The SP_MIN setup function. Calls platforms init functions
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*****************************************************************************/
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void sp_min_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
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u_register_t arg3)
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{
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/* Enable early console if EARLY_CONSOLE flag is enabled */
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plat_setup_early_console();
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/* Perform early platform-specific setup */
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sp_min_early_platform_setup2(arg0, arg1, arg2, arg3);
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sp_min_plat_arch_setup();
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}
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/******************************************************************************
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* The SP_MIN main function. Do the platform and PSCI Library setup. Also
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* initialize the runtime service framework.
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*****************************************************************************/
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void sp_min_main(void)
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{
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NOTICE("SP_MIN: %s\n", build_version_string);
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NOTICE("SP_MIN: %s\n", build_message);
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/* Perform the SP_MIN platform setup */
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sp_min_platform_setup();
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/* Initialize the runtime services e.g. psci */
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INFO("SP_MIN: Initializing runtime services\n");
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runtime_svc_init();
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/*
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* We are ready to enter the next EL. Prepare entry into the image
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* corresponding to the desired security state after the next ERET.
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*/
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sp_min_prepare_next_image_entry();
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/*
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* Perform any platform specific runtime setup prior to cold boot exit
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* from SP_MIN.
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*/
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sp_min_plat_runtime_setup();
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console_flush();
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console_switch_state(CONSOLE_FLAG_RUNTIME);
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}
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/******************************************************************************
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* This function is invoked during warm boot. Invoke the PSCI library
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* warm boot entry point which takes care of Architectural and platform setup/
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* restore. Copy the relevant cpu_context register values to smc context which
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* will get programmed during `smc_exit`.
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*****************************************************************************/
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void sp_min_warm_boot(void)
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{
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smc_ctx_t *next_smc_ctx;
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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u_register_t ns_sctlr;
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psci_warmboot_entrypoint();
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smc_set_next_ctx(NON_SECURE);
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next_smc_ctx = smc_get_next_ctx();
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zeromem(next_smc_ctx, sizeof(smc_ctx_t));
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copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
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next_smc_ctx);
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/* Temporarily set the NS bit to access NS SCTLR */
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write_scr(read_scr() | SCR_NS_BIT);
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isb();
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ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
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write_sctlr(ns_sctlr);
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isb();
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write_scr(read_scr() & ~SCR_NS_BIT);
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isb();
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}
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#if SP_MIN_WITH_SECURE_FIQ
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/******************************************************************************
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* This function is invoked on secure interrupts. By construction of the
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* SP_MIN, secure interrupts can only be handled when core executes in non
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* secure state.
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*****************************************************************************/
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void sp_min_fiq(void)
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{
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uint32_t id;
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id = plat_ic_acknowledge_interrupt();
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sp_min_plat_fiq_handler(id);
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plat_ic_end_of_interrupt(id);
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}
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#endif /* SP_MIN_WITH_SECURE_FIQ */
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