Bipin Ravi 3f9df2c6ad fix(cpus): workaround for Cortex-X3 erratum 2302506 ... Cortex-X3 erratum 2302506 is a cat B erratum that applies to revisions r0p0-r1p1 and is fixed in r1p2. The workaround is to set bit[0] of CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidation to other PE caches. There might be a small performance degradation to this workaround for certain workloads that share data. SDEN can be found here: https://developer.arm.com/documentation/2055130/latest Change-Id: I048b830867915b88afa36582c6da05734a56d22a Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>		2024-01-17 14:22:21 -06:00
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aarch32	refactor(cpus): add Cortex-A57 errata framework information	2023-08-24 14:27:42 -05:00
aarch64	fix(cpus): workaround for Cortex-X3 erratum 2302506	2024-01-17 14:22:21 -06:00
cpu-ops.mk	fix(cpus): workaround for Cortex-X3 erratum 2302506	2024-01-17 14:22:21 -06:00
errata_report.c	fix(cpus): reduce generic_errata_report()'s size	2023-06-15 10:14:59 +01:00