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3f3c341ae5
There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.
Before: ENABLE_SPM=1 is required for using either implementation.
By default, the SPCI-based implementation is enabled and
this is overridden if SPM_MM=1.
After: ENABLE_SPM=1 enables the SPCI-based implementation.
SPM_MM=1 enables the MM-based implementation.
The two build flags are mutually exclusive.
Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.
Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/*
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/ccn.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <drivers/arm/sbsa.h>
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#include <sgi_base_platform_def.h>
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#include <services/secure_partition.h>
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#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
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V2M_FLASH0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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/*
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* Table of regions for different BL stages to map using the MMU.
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* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
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* arm_configure_mmu_elx() will give the available subset of that.
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*
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* Replace or extend the below regions as required
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*/
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#if IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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SGI_MAP_FLASH0_RO,
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CSS_SGI_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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{0}
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};
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#endif
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#if IMAGE_BL2
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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SGI_MAP_FLASH0_RO,
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CSS_SGI_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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ARM_MAP_NS_DRAM1,
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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#if SPM_MM
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ARM_SP_IMAGE_MMAP,
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#endif
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#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
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ARM_MAP_BL1_RW,
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#endif
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{0}
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};
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#endif
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#if IMAGE_BL31
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_IOFPGA,
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CSS_SGI_MAP_DEVICE,
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SOC_CSS_MAP_DEVICE,
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#if SPM_MM
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ARM_SPM_BUF_EL3_MMAP,
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#endif
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{0}
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};
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#if SPM_MM && defined(IMAGE_BL31)
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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PLAT_ARM_SECURE_MAP_DEVICE,
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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ARM_SP_CPER_BUF_MMAP,
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ARM_SP_IMAGE_RW_MMAP,
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ARM_SPM_BUF_EL0_MMAP,
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{0}
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};
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#endif /* SPM_MM && defined(IMAGE_BL31) */
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#endif
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ARM_CASSERT_MMAP
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#if SPM_MM && defined(IMAGE_BL31)
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/*
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* Boot information passed to a secure partition during initialisation. Linear
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* indices in MP information will be filled at runtime.
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*/
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static secure_partition_mp_info_t sp_mp_info[] = {
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[0] = {0x81000000, 0},
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[1] = {0x81000100, 0},
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[2] = {0x81000200, 0},
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[3] = {0x81000300, 0},
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[4] = {0x81010000, 0},
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[5] = {0x81010100, 0},
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[6] = {0x81010200, 0},
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[7] = {0x81010300, 0},
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};
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const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(secure_partition_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = ARM_SP_IMAGE_BASE,
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.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
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.sp_image_base = ARM_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = ARM_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = &sp_mp_info[0],
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};
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const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_arm_secure_partition_mmap;
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}
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const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
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void *cookie)
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{
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return &plat_arm_secure_partition_boot_info;
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}
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#endif /* SPM_MM && defined(IMAGE_BL31) */
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#if TRUSTED_BOARD_BOOT
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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void plat_arm_secure_wdt_start(void)
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{
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sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
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}
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