johpow01 3f0d83695c Workaround for Cortex A76 erratum 1946160 ... Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327		2020-12-18 17:41:23 +00:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	Workaround for Cortex A76 erratum 1946160	2020-12-18 17:41:23 +00:00
firmware-design.rst	doc: Correct CPACR.FPEN usage	2020-09-14 02:35:50 +00:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	Update cryptographic algorithms in TBBR doc	2020-03-12 17:11:25 +01:00