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https://github.com/ARM-software/arm-trusted-firmware.git
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3dcb94dd84
Add bridge enablement features for each platform. The bridge access will be enabled automatically for FPGA 1st configuration only. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
92 lines
3.6 KiB
C
92 lines
3.6 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_SYSTEMMANAGER_H
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#define AGX_SYSTEMMANAGER_H
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#define AGX_FIREWALL_SOC2FPGA 0xffd21200
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#define AGX_FIREWALL_LWSOC2FPGA 0xffd21300
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#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
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#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
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#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
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#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
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#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
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#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
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#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
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#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
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#define AGX_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
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#define AGX_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
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#define AGX_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
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#define AGX_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
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#define AGX_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
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#define AGX_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
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#define AGX_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
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#define AGX_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
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#define AGX_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
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#define AGX_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
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#define AGX_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
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#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
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#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
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#define AGX_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
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#define AGX_NOC_FW_L4_PER_SCR_UART1 0xffd21070
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#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
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#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
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#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
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#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
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#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
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#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
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#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
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#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
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#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
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#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
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#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
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#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
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#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
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#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
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#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
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#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
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#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
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#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
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#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
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#define AGX_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
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#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
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#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
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#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
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#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
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#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
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#define SYSMGR_NOC_TIMEOUT 0xc0
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#define SYSMGR_NOC_IDLEREQ_SET 0xc4
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#define SYSMGR_NOC_IDLEREQ_CLR 0xc8
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#define SYSMGR_NOC_IDLEREQ_VAL 0xcc
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#define SYSMGR_NOC_IDLEACK 0xd0
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#define SYSMGR_NOC_IDLESTATUS 0xd4
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#define IDLE_DATA_LWSOC2FPGA BIT(0)
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#define IDLE_DATA_SOC2FPGA BIT(4)
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#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
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#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
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#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
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#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
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#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
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#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
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void enable_nonsecure_access(void);
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void enable_ns_peripheral_access(void);
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void enable_ns_bridge_access(void);
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#endif
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