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777f1f6897
spe_disable function, disables profiling and flushes all the buffers and hence needs to be called on power-off/suspend path. It needs to be invoked as SPE feature writes to memory as part of regular operation and not disabling before exiting coherency could potentially cause issues. Currently, this is handled only for the FVP. Other platforms need to replicate this behaviour and is covered as part of this patch. Calling it from generic psci library code, before the platform specific actions to turn off the CPUs, will make it applicable for all the platforms which have ported the PSCI library. Change-Id: I90b24c59480357e2ebfa3dfc356c719ca935c13d Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
131 lines
2.8 KiB
C
131 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/spe.h>
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#include <plat/common/platform.h>
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typedef struct spe_ctx {
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u_register_t pmblimitr_el1;
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} spe_ctx_t;
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static struct spe_ctx spe_ctxs[PLATFORM_CORE_COUNT];
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static inline void psb_csync(void)
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{
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/*
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* The assembler does not yet understand the psb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #17");
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}
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void spe_init_el3(void)
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{
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uint64_t v;
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/*
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* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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*
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* MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
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* When FEAT_RME is not implemented, this field is RES0.
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*
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* MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
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* register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
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* Setting this bit to 1 doesn't have any effect on it when
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* FEAT_SPEv1p2 not implemented.
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*/
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v = read_mdcr_el3();
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v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
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v &= ~(MDCR_NSPBE_BIT);
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write_mdcr_el3(v);
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}
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void spe_init_el2_unused(void)
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{
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uint64_t v;
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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void spe_disable(void)
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{
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uint64_t v;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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static void *spe_drain_buffers_hook(const void *arg)
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{
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if (!is_feat_spe_supported())
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return (void *)-1;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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return (void *)0;
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}
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static void *spe_context_save(const void *arg)
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{
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unsigned int core_pos;
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struct spe_ctx *ctx;
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if (is_feat_spe_supported()) {
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core_pos = plat_my_core_pos();
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ctx = &spe_ctxs[core_pos];
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ctx->pmblimitr_el1 = read_pmblimitr_el1();
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}
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return NULL;
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}
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static void *spe_context_restore(const void *arg)
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{
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unsigned int core_pos;
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struct spe_ctx *ctx;
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if (is_feat_spe_supported()) {
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core_pos = plat_my_core_pos();
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ctx = &spe_ctxs[core_pos];
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write_pmblimitr_el1(ctx->pmblimitr_el1);
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}
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return NULL;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, spe_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, spe_context_restore);
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