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3d5ed6dee2
When using the SPM Dispatcher, the SPMC sits as a BL32 component (BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw config component (TOS_FW_CONFIG_ID). It defines platform specific attributes (memory range and physical CPU layout) as well as the attributes for each secure partition (mostly load address). This manifest is passed to the SPMC on boot up. An SP package contains the SP dtb in the SPCI defined partition manifest format. As the SPMC manifest was enriched it needs an increase of tos_fw-config max-size in fvp_fw_config dts. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ia1dce00c6c4cbaa118fa56617980d32e2956a94e
67 lines
1.1 KiB
Text
67 lines
1.1 KiB
Text
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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compatible = "arm,spci-core-manifest-1.0";
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attribute {
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spmc_id = <0x8000>;
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maj_ver = <0x0>;
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min_ver = <0x9>;
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exec_state = <0x0>;
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load_address = <0x0 0x6000000>;
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entrypoint = <0x0 0x6000000>;
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};
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chosen {
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linux,initrd-start = <0>;
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linux,initrd-end = <0>;
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};
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hypervisor {
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compatible = "hafnium,hafnium";
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vm1 {
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is_spci_partition;
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debug_name = "cactus-primary";
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load-addr = <0x7000000>;
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};
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vm2 {
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is_spci_partition;
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debug_name = "cactus-secondary";
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load-addr = <0x7100000>;
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vcpu_count = <2>;
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mem_size = <1048576>;
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};
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x2>;
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};
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};
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};
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <0xc>;
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phandle = <0x2>;
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};
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x6000000 0x2000000>; /* Trusted DRAM */
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};
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};
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