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https://github.com/ARM-software/arm-trusted-firmware.git
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3cc17aae72
This patch implements CSS platform hook to support NODE_HW_STATE PSCI API. The platform hook queries SCP to obtain CSS power state. Power states returned by SCP are then converted to expected PSCI return codes. Juno's PSCI operation structure is modified to use the CSS implementation. Change-Id: I4a5edac0e5895dd77b51398cbd78f934831dafc0
162 lines
5.5 KiB
C
162 lines
5.5 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CSS_DEF_H__
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#define __CSS_DEF_H__
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#include <arm_def.h>
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#include <tzc400.h>
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/*************************************************************************
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* Definitions common to all ARM Compute SubSystems (CSS)
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*************************************************************************/
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#define NSROM_BASE 0x1f000000
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#define NSROM_SIZE 0x00001000
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/* Following covers CSS Peripherals excluding NSROM and NSRAM */
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#define CSS_DEVICE_BASE 0x20000000
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#define CSS_DEVICE_SIZE 0x0e000000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x00008000
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/* System Security Control Registers */
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#define SSC_REG_BASE 0x2a420000
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#define SSC_GPRETN (SSC_REG_BASE + 0x030)
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/* The slave_bootsecure controls access to GPU, DMC and CS. */
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#define CSS_NIC400_SLAVE_BOOTSECURE 8
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/* Interrupt handling constants */
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#define CSS_IRQ_MHU 69
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#define CSS_IRQ_GPU_SMMU_0 71
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#define CSS_IRQ_TZC 80
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#define CSS_IRQ_TZ_WDOG 86
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#define CSS_IRQ_SEC_SYS_TIMER 91
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/*
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* Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
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* GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
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*/
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#define CSS_G1S_IRQS CSS_IRQ_MHU, \
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CSS_IRQ_GPU_SMMU_0, \
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CSS_IRQ_TZC, \
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CSS_IRQ_TZ_WDOG, \
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CSS_IRQ_SEC_SYS_TIMER
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/*
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* SCP <=> AP boot configuration
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*
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* The SCP/AP boot configuration is a 32-bit word located at a known offset from
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* the start of the Trusted SRAM.
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*
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* Note that the value stored at this address is only valid at boot time, before
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* the SCP_BL2 image is transferred to SCP.
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*/
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#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
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#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
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CSS_DEVICE_BASE, \
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CSS_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* Platform ID address */
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#define SSC_VERSION_OFFSET 0x040
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#define SSC_VERSION_CONFIG_SHIFT 28
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#define SSC_VERSION_MAJOR_REV_SHIFT 24
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#define SSC_VERSION_MINOR_REV_SHIFT 20
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#define SSC_VERSION_DESIGNER_ID_SHIFT 12
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#define SSC_VERSION_PART_NUM_SHIFT 0x0
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#define SSC_VERSION_CONFIG_MASK 0xf
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#define SSC_VERSION_MAJOR_REV_MASK 0xf
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#define SSC_VERSION_MINOR_REV_MASK 0xf
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#define SSC_VERSION_DESIGNER_ID_MASK 0xff
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#define SSC_VERSION_PART_NUM_MASK 0xfff
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#ifndef __ASSEMBLY__
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/* SSC_VERSION related accessors */
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/* Returns the part number of the platform */
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#define GET_SSC_VERSION_PART_NUM(val) \
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(((val) >> SSC_VERSION_PART_NUM_SHIFT) & \
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SSC_VERSION_PART_NUM_MASK)
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/* Returns the configuration number of the platform */
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#define GET_SSC_VERSION_CONFIG(val) \
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(((val) >> SSC_VERSION_CONFIG_SHIFT) & \
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SSC_VERSION_CONFIG_MASK)
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#endif /* __ASSEMBLY__ */
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/*************************************************************************
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* Required platform porting definitions common to all
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* ARM Compute SubSystems (CSS)
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************************************************************************/
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/*
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* The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there
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* respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE).
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* Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load
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* an SCP_BL2/SCP_BL2U image.
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*/
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#if CSS_LOAD_SCP_IMAGES
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/*
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* Load address of SCP_BL2 in CSS platform ports
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* SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the
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* SCP, it is discarded and BL31 is loaded over the top.
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*/
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#define SCP_BL2_BASE BL31_BASE
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#define SCP_BL2U_BASE BL31_BASE
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#endif /* CSS_LOAD_SCP_IMAGES */
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/* Load address of Non-Secure Image for CSS platform ports */
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#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
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/* TZC related constants */
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
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/* Trusted mailbox base address common to all CSS */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/*
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* Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
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* command
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*/
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#define CSS_CLUSTER_PWR_STATE_ON 0
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#define CSS_CLUSTER_PWR_STATE_OFF 3
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#define CSS_CPU_PWR_STATE_ON 1
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#define CSS_CPU_PWR_STATE_OFF 0
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#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1)
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#endif /* __CSS_DEF_H__ */
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