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5dffb46c9c
This patch re-factors the following headers to make it easier to
integrate the PSCI library with an AArch32 Secure Payload :
* bl_common.h : The entry point information and the param
header data structures are factored out into separate
headers ep_info.h and param_headers.h
* psci.h : The PSCI library interfaces are factored out
into the new header psci_lib.h
* context_mgmt.h : The header file is modified to not include
arch.h when compiled for AArch32 mode.
No functional changes are introduced by this patch.
Change-Id: I5e21a843c0af2ba8e47dee4e577cf95929be8cd4
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
145 lines
4.9 KiB
C
145 lines
4.9 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __EP_INFO_H__
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#define __EP_INFO_H__
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#include <param_header.h>
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#define SECURE 0x0
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#define NON_SECURE 0x1
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#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
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/*******************************************************************************
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* Constants that allow assembler code to access members of and the
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* 'entry_point_info' structure at their correct offsets.
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******************************************************************************/
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#define ENTRY_POINT_INFO_PC_OFFSET 0x08
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#ifdef AARCH32
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#define ENTRY_POINT_INFO_ARGS_OFFSET 0x10
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#else
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#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18
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#endif
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/* The following are used to set/get image attributes. */
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#define PARAM_EP_SECURITY_MASK (0x1)
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#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
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#define SET_SECURITY_STATE(x, security) \
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((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
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#define EP_EE_MASK 0x2
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#define EP_EE_LITTLE 0x0
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#define EP_EE_BIG 0x2
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#define EP_GET_EE(x) (x & EP_EE_MASK)
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#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
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#define EP_ST_MASK 0x4
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#define EP_ST_DISABLE 0x0
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#define EP_ST_ENABLE 0x4
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#define EP_GET_ST(x) (x & EP_ST_MASK)
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#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
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#define EP_EXE_MASK 0x8
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#define NON_EXECUTABLE 0x0
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#define EXECUTABLE 0x8
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#define EP_GET_EXE(x) (x & EP_EXE_MASK)
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#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
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#define EP_FIRST_EXE_MASK 0x10
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#define EP_FIRST_EXE 0x10
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#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK)
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#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee))
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <types.h>
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typedef struct aapcs64_params {
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u_register_t arg0;
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u_register_t arg1;
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u_register_t arg2;
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u_register_t arg3;
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u_register_t arg4;
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u_register_t arg5;
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u_register_t arg6;
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u_register_t arg7;
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} aapcs64_params_t;
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typedef struct aapcs32_params {
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u_register_t arg0;
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u_register_t arg1;
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u_register_t arg2;
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u_register_t arg3;
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} aapcs32_params_t;
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/*****************************************************************************
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* This structure represents the superset of information needed while
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* switching exception levels. The only two mechanisms to do so are
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* ERET & SMC. Security state is indicated using bit zero of header
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* attribute
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* NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
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* of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
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* processing SMC to jump to BL31.
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*****************************************************************************/
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typedef struct entry_point_info {
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param_header_t h;
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uintptr_t pc;
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uint32_t spsr;
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#ifdef AARCH32
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aapcs32_params_t args;
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#else
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aapcs64_params_t args;
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#endif
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} entry_point_info_t;
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/*
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* Compile time assertions related to the 'entry_point_info' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(ENTRY_POINT_INFO_PC_OFFSET ==
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__builtin_offsetof(entry_point_info_t, pc), \
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assert_BL31_pc_offset_mismatch);
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CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \
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__builtin_offsetof(entry_point_info_t, args), \
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assert_BL31_args_offset_mismatch);
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CASSERT(sizeof(uintptr_t) ==
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__builtin_offsetof(entry_point_info_t, spsr) - \
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__builtin_offsetof(entry_point_info_t, pc), \
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assert_entrypoint_and_spsr_should_be_adjacent);
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#endif /*__ASSEMBLY__*/
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#endif /* __EP_INFO_H__ */
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